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msr.h
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/*
Copyright (c) 2012, Intel Corporation
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
* Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* Written by Martin Dimitrov, Carl Strickland */
#ifndef _h_msr_t
#define _h_msr_t
#include <stdint.h>
#define MY_ERROR -1
/* Replacement for pow() where the base is 2 and the power is unsigned and
* less than 31 (will get invalid numbers if 31 or greater) */
#define B2POW(e) (((e) == 0) ? 1 : (2 << ((e) - 1)))
/* General (Sandy Bridge Client/Server) */
#define MSR_RAPL_POWER_UNIT 0x606 /* Unit Multiplier used in RAPL Interfaces (R/O) */
/* Platform (Supported by 6th Generation Intel® Core™ Processors and the Intel® Xeon® Processor
* Scalable Family Based on Skylake Microarchitecture, 7th Generation Intel® Core™ Processors Based on Kaby Lake
* Microarchitecture, 8th Generation and 9th Generation Intel® Core™ Processors and Intel® Xeon® E Processors Based
* on Coffee Lake Microarchitecture, and 8th Generation Intel® Core™ i3 Processors Based on Cannon Lake
* Microarchitecture)
* Platform Energy Counter (R/O). This MSR is valid only if both platform vendor hardware
* implementation and BIOS enablement support it. This MSR will read 0 if not valid.
*
* The notation of “Platform” in the Scope column (with respect to MSR_PLATFORM_ENERGY_COUNTER and
* MSR_PLATFORM_POWER_LIMIT) is limited to the power-delivery domain and the specifics of the power delivery
* integration may vary by platform vendor’s implementation.
*/
#define MSR_PLATFORM_ENERGY_COUNTER 0x64d /* Platform Energy Status (R/O) */
#define MSR_PLATFORM_POWER_LIMIT 0x65c /* Platform Power Limit Control (R/W) */
/* PKG (Sandy Bridge Client/Server) */
#define MSR_RAPL_PKG_POWER_LIMIT 0x610 /* PKG RAPL Power Limit Control (R/W) */
#define MSR_RAPL_PKG_ENERGY_STATUS 0x611 /* PKG Energy Status (R/O) */
#define MSR_RAPL_PKG_PERF_STATUS 0x613 /* PKG Performance Throttling Status (R/O) */
#define MSR_RAPL_PKG_POWER_INFO 0x614 /* PKG RAPL Parameters (R/O) */
/* DRAM (Sandy Bridge Server) */
#define MSR_RAPL_DRAM_POWER_LIMIT 0x618 /* DRAM RAPL Power Limit Control (R/W) */
#define MSR_RAPL_DRAM_ENERGY_STATUS 0x619 /* DRAM Energy Status (R/O) */
#define MSR_RAPL_DRAM_PERF_STATUS 0x61b /* DRAM Performance Throttling Status (R/O) */
#define MSR_RAPL_DRAM_POWER_INFO 0x61c /* DRAM RAPL Parameters (R/O) */
/* PP0 (Sandy Bridge Client/Server) */
#define MSR_RAPL_PP0_POWER_LIMIT 0x638 /* PP0 RAPL Power Limit Control (R/W) */
#define MSR_RAPL_PP0_ENERGY_STATUS 0x639 /* PP0 Energy Status (R/O) */
#define MSR_RAPL_PP0_POLICY 0x63a /* PP0 Performance Throttling Status (R/O) */
#define MSR_RAPL_PP0_PERF_STATUS 0x63b /* PP0 Balance Policy (R/W) */
/* PP1 (Sandy Bridge Gen2 Client) */
#define MSR_RAPL_PP1_POWER_LIMIT 0x640 /* PP1 RAPL Power Limit Control (R/W) */
#define MSR_RAPL_PP1_ENERGY_STATUS 0x641 /* PP1 Energy Status (R/O) */
#define MSR_RAPL_PP1_POLICY 0x642 /* PP1 Balance Policy (R/W) */
/* Common MSR Structures */
typedef struct rapl_power_limit_control_msr_t {
unsigned int power_limit : 15;
unsigned int limit_enabled : 1;
unsigned int clamp_enabled : 1;
unsigned int limit_time_window_y : 5;
unsigned int limit_time_window_f : 2;
unsigned int : 7;
unsigned int lock_enabled : 1;
unsigned int : 32;
} rapl_power_limit_control_msr_t;
/* Wrap-around time of many hours. */
typedef struct rapl_parameters_msr_t {
unsigned int thermal_spec_power : 15;
unsigned int : 1;
unsigned int minimum_power : 15;
unsigned int : 1;
unsigned int maximum_power : 15;
unsigned int : 1;
unsigned int maximum_limit_time_window : 6;
unsigned int : 10;
} rapl_parameters_msr_t;
/* Updated every ~1ms. Wraparound time of 60s under load. */
typedef struct energy_status_msr_t {
unsigned int total_energy_consumed : 32;
unsigned int : 32;
} energy_status_msr_t;
typedef struct performance_throttling_status_msr_t {
unsigned int accumulated_throttled_time : 32;
unsigned int : 32;
} performance_throttling_status_msr_t;
typedef struct balance_policy_msr_t {
unsigned int priority_level : 5;
unsigned int : 32;
unsigned int : 27;
} balance_policy_msr_t;
/* General */
typedef struct rapl_unit_multiplier_msr_t {
unsigned int power : 4;
unsigned int : 4;
unsigned int energy : 5;
unsigned int : 3;
unsigned int time : 4;
unsigned int : 32;
unsigned int : 12;
} rapl_unit_multiplier_msr_t;
/* PLATFORM */
typedef struct platform_power_limit_control_msr_t {
unsigned int power_limit_1 : 15;
unsigned int limit_enabled_1 : 1;
unsigned int clamp_enabled_1 : 1;
unsigned int limit_time_window_y_1 : 5;
unsigned int limit_time_window_f_1 : 2;
unsigned int : 8;
unsigned int power_limit_2 : 15;
unsigned int limit_enabled_2 : 1;
unsigned int clamp_enabled_2 : 1;
unsigned int : 14;
unsigned int lock_enabled : 1;
} platform_power_limit_control_msr_t;
/* PKG */
typedef struct pkg_rapl_power_limit_control_msr_t {
unsigned int power_limit_1 : 15;
unsigned int limit_enabled_1 : 1;
unsigned int clamp_enabled_1 : 1;
unsigned int limit_time_window_y_1 : 5;
unsigned int limit_time_window_f_1 : 2;
unsigned int : 8;
unsigned int power_limit_2 : 15;
unsigned int limit_enabled_2 : 1;
unsigned int clamp_enabled_2 : 1;
unsigned int limit_time_window_y_2 : 5;
unsigned int limit_time_window_f_2 : 2;
unsigned int : 7;
unsigned int lock_enabled : 1;
} pkg_rapl_power_limit_control_msr_t;
typedef energy_status_msr_t pkg_energy_status_msr_t;
typedef rapl_parameters_msr_t pkg_rapl_parameters_msr_t;
typedef performance_throttling_status_msr_t pkg_performance_throttling_status_msr_t;
/* PP0 */
typedef rapl_power_limit_control_msr_t pp0_rapl_power_limit_control_msr_t;
typedef energy_status_msr_t pp0_energy_status_msr_t;
typedef balance_policy_msr_t pp0_balance_policy_msr_t;
typedef performance_throttling_status_msr_t pp0_performance_throttling_status_msr_t;
/* PP1 */
typedef rapl_power_limit_control_msr_t pp1_rapl_power_limit_control_msr_t;
typedef energy_status_msr_t pp1_energy_status_msr_t;
typedef balance_policy_msr_t pp1_balance_policy_msr_t;
typedef performance_throttling_status_msr_t pp1_performance_throttling_status_msr_t;
/* DRAM */
typedef rapl_power_limit_control_msr_t dram_rapl_power_limit_control_msr_t;
typedef energy_status_msr_t dram_energy_status_msr_t;
typedef rapl_parameters_msr_t dram_rapl_parameters_msr_t;
typedef performance_throttling_status_msr_t dram_performance_throttling_status_msr_t;
/*
* For documentaion see: "Intel64 and IA-32 Architectures Software Developer's Manual" Volume 3B, Appendix B Model-Specific registers.
* http://www.intel.com/Assets/PDF/manual/253669.pdf In a nutshell, search the manual and find the MSR number that you wish to read/write.
* Then use the read_msr_t/write_msr_t functions and extract_bit functions to get the info you need.
*/
/**
* Read the given MSR on the given CPU.
*
* @return 0 on success and MY_ERROR on failure
*/
int read_msr(int cpu, unsigned int address, uint64_t *val);
/**
* Write the given value to the given MSR on the given CPU.
*
* @return 0 on success and MY_ERROR on failure
*/
int write_msr(int cpu, unsigned int address, uint64_t val);
#endif