diff --git a/sycl/doc/extensions/DataFlowPipes/data_flow_pipes_rev4_proposed.asciidoc b/sycl/doc/extensions/proposed/SYCL_EXT_INTEL_DATAFLOW_PIPES.asciidoc old mode 100755 new mode 100644 similarity index 99% rename from sycl/doc/extensions/DataFlowPipes/data_flow_pipes_rev4_proposed.asciidoc rename to sycl/doc/extensions/proposed/SYCL_EXT_INTEL_DATAFLOW_PIPES.asciidoc index 4b8cbc5dffb1f..4bf496b1d2acd --- a/sycl/doc/extensions/DataFlowPipes/data_flow_pipes_rev4_proposed.asciidoc +++ b/sycl/doc/extensions/proposed/SYCL_EXT_INTEL_DATAFLOW_PIPES.asciidoc @@ -17,7 +17,11 @@ :language: {basebackend@docbook:c++:cpp} == Introduction -IMPORTANT: This specification is a draft. +IMPORTANT: This is a proposed update to an existing extension. The APIs +described in this document are not yet implemented and cannot be used in +application code. See +link:../supported/SYCL_EXT_INTEL_DATAFLOW_PIPES.asciidoc[here] for the existing +extension, which is implemented. NOTE: Khronos(R) is a registered trademark and SYCL(TM) and SPIR(TM) are trademarks of The Khronos Group Inc. OpenCL(TM) is a trademark of Apple Inc. used by permission by Khronos. diff --git a/sycl/doc/extensions/IntelFPGA/FPGALsu_rev2_proposed.md b/sycl/doc/extensions/proposed/SYCL_EXT_INTEL_FPGA_LSU.md similarity index 97% rename from sycl/doc/extensions/IntelFPGA/FPGALsu_rev2_proposed.md rename to sycl/doc/extensions/proposed/SYCL_EXT_INTEL_FPGA_LSU.md index ad85bee3af4bf..88ce1ef826819 100644 --- a/sycl/doc/extensions/IntelFPGA/FPGALsu_rev2_proposed.md +++ b/sycl/doc/extensions/proposed/SYCL_EXT_INTEL_FPGA_LSU.md @@ -1,6 +1,13 @@ # FPGA lsu +**IMPORTANT:** This is a proposed update to an existing extension. The APIs +described in this document are not yet implemented and cannot be used in +application code. See [here][1] for the existing extension, which is +implemented. + +[1]: <../supported/SYCL_EXT_INTEL_FPGA_LSU.md> + The Intel FPGA `lsu` class is implemented in `sycl/ext/intel/fpga_lsu.hpp` which is included in `sycl/ext/intel/fpga_extensions.hpp`.