From 6fad3fa2109b6730442d13846c7ed507cedecb9d Mon Sep 17 00:00:00 2001 From: Jakub Chlanda Date: Fri, 21 Jan 2022 08:13:35 -0500 Subject: [PATCH] [SYCL] Make sure [AMDGPU|NVPTX]CodeGen links in lower SYCL IR passes --- llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 + llvm/lib/Target/NVPTX/CMakeLists.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/CMakeLists.txt b/llvm/lib/Target/AMDGPU/CMakeLists.txt index ca5208355db96..ce8bb2e06df87 100644 --- a/llvm/lib/Target/AMDGPU/CMakeLists.txt +++ b/llvm/lib/Target/AMDGPU/CMakeLists.txt @@ -176,6 +176,7 @@ add_llvm_target(AMDGPUCodeGen GlobalISel BinaryFormat MIRParser + SYCLLowerIR ADD_TO_COMPONENT AMDGPU diff --git a/llvm/lib/Target/NVPTX/CMakeLists.txt b/llvm/lib/Target/NVPTX/CMakeLists.txt index e5a4eb43b912d..8c53d3173f4ff 100644 --- a/llvm/lib/Target/NVPTX/CMakeLists.txt +++ b/llvm/lib/Target/NVPTX/CMakeLists.txt @@ -58,6 +58,7 @@ add_llvm_target(NVPTXCodeGen TransformUtils Vectorize Passes + SYCLLowerIR ADD_TO_COMPONENT NVPTX