From a7fb508514406a179bd50dffb705d5757c7d0bb9 Mon Sep 17 00:00:00 2001 From: Premanand M Rao Date: Wed, 12 Mar 2025 19:56:02 -0700 Subject: [PATCH] Resolve test failures --- clang/lib/CodeGen/CGExprScalar.cpp | 4 +++- clang/test/CodeGenSYCL/address-space-cond-op.cpp | 2 +- clang/test/CodeGenSYCL/address-space-of-returns.cpp | 2 +- clang/test/CodeGenSYCL/nvptx-short-ptr.cpp | 6 +++--- clang/test/CodeGenSYCL/regcall-cc-test.cpp | 2 +- clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp | 2 +- 6 files changed, 10 insertions(+), 8 deletions(-) diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 053e87c7bd94d..c4c5cb25f788b 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -2375,10 +2375,12 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { llvm::Type *DstTy = ConvertType(DestTy); if (SrcTy->isPointerTy() && DstTy->isPointerTy() && - SrcTy->getPointerAddressSpace() != DstTy->getPointerAddressSpace()) + SrcTy->getPointerAddressSpace() != DstTy->getPointerAddressSpace()) { Src = Builder.CreateAddrSpaceCast( Src, llvm::PointerType::get(VMContext, DstTy->getPointerAddressSpace())); + SrcTy = Src->getType(); + } // FIXME: this is a gross but seemingly necessary workaround for an issue // manifesting when a target uses a non-default AS for indirect sret args, diff --git a/clang/test/CodeGenSYCL/address-space-cond-op.cpp b/clang/test/CodeGenSYCL/address-space-cond-op.cpp index 3fe630ca19c94..db2b2f57e4bda 100644 --- a/clang/test/CodeGenSYCL/address-space-cond-op.cpp +++ b/clang/test/CodeGenSYCL/address-space-cond-op.cpp @@ -25,7 +25,7 @@ struct S { // CHECK-NEXT: br label [[COND_END]] // CHECK: cond.end: // CHECK-NEXT: [[COND_LVALUE:%.*]] = phi ptr addrspace(4) [ [[TMP1]], [[COND_TRUE]] ], [ [[RHS_ASCAST]], [[COND_FALSE]] ] -// CHECK-NEXT: call void @llvm.memcpy.p4.p4.i64(ptr addrspace(4) align 2 [[AGG_RESULT:%.*]], ptr addrspace(4) align 2 [[COND_LVALUE]], i64 2, i1 false) +// CHECK-NEXT: call void @llvm.memcpy.p0.p4.i64(ptr align 2 [[AGG_RESULT:%.*]], ptr addrspace(4) align 2 [[COND_LVALUE]], i64 2, i1 false) // CHECK-NEXT: ret void // S foo(bool cond, S &lhs, S rhs) { diff --git a/clang/test/CodeGenSYCL/address-space-of-returns.cpp b/clang/test/CodeGenSYCL/address-space-of-returns.cpp index 37e1b4d194ea0..017a09750f9d9 100644 --- a/clang/test/CodeGenSYCL/address-space-of-returns.cpp +++ b/clang/test/CodeGenSYCL/address-space-of-returns.cpp @@ -25,7 +25,7 @@ A ret_agg() { A a; return a; } -// CHECK: define {{.*}}spir_func void @{{.*}}ret_agg{{.*}}(ptr addrspace(4) dead_on_unwind noalias writable sret(%struct{{.*}}.A) align 4 %agg.result) +// CHECK: define {{.*}}spir_func void @{{.*}}ret_agg{{.*}}(ptr dead_on_unwind noalias writable sret(%struct{{.*}}.A) align 4 %agg.result) template __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) { diff --git a/clang/test/CodeGenSYCL/nvptx-short-ptr.cpp b/clang/test/CodeGenSYCL/nvptx-short-ptr.cpp index 5820905d6ea00..1cbf8f74c9a9a 100644 --- a/clang/test/CodeGenSYCL/nvptx-short-ptr.cpp +++ b/clang/test/CodeGenSYCL/nvptx-short-ptr.cpp @@ -20,9 +20,9 @@ // Targeting a 32-bit NVPTX, check that we see universal 32-bit pointers (the // option changes nothing) -// CHECK32: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64" +// CHECK32: target datalayout = "e-p:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64" // Targeting a 64-bit NVPTX target, check that we see 32-bit pointers for // shared (3), const (4), and local (5) address spaces only. -// CHECK64-DEFAULT: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64" -// CHECK64-SHORT: target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64" +// CHECK64-DEFAULT: target datalayout = "e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64" +// CHECK64-SHORT: target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64" diff --git a/clang/test/CodeGenSYCL/regcall-cc-test.cpp b/clang/test/CodeGenSYCL/regcall-cc-test.cpp index 1c3a4ef0f0ab6..8f5dd318b8ea2 100644 --- a/clang/test/CodeGenSYCL/regcall-cc-test.cpp +++ b/clang/test/CodeGenSYCL/regcall-cc-test.cpp @@ -333,7 +333,7 @@ struct NonCopyable { // CHECK-DAG: %struct.NonCopyable = type { i32 } SYCL_DEVICE int __regcall bar(NonCopyable x) { -// CHECK-DAG: define dso_local x86_regcallcc noundef i32 @_Z15__regcall3__bar11NonCopyable(ptr noundef %x) +// CHECK-DAG: define dso_local x86_regcallcc noundef i32 @_Z15__regcall3__bar11NonCopyable(ptr noundef byval(%struct.NonCopyable) align 4 %x) return x.a; } diff --git a/clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp b/clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp index bb5a93759ea9f..56f70767b8804 100644 --- a/clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp +++ b/clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp @@ -7,7 +7,7 @@ #include "Inputs/sycl.hpp" -// CHECK: define{{.*}} void @_Z3fooDB4096_S_(ptr addrspace(4) {{.*}} sret(i4096) align 8 %agg.result, ptr {{.*}} byval(i4096) align 8 %[[ARG1:[0-9]+]], ptr {{.*}} byval(i4096) align 8 %[[ARG2:[0-9]+]]) +// CHECK: define{{.*}} void @_Z3fooDB4096_S_(ptr {{.*}} sret(i4096) align 8 %agg.result, ptr {{.*}} byval(i4096) align 8 %[[ARG1:[0-9]+]], ptr {{.*}} byval(i4096) align 8 %[[ARG2:[0-9]+]]) signed _BitInt(4096) foo(signed _BitInt(4096) a, signed _BitInt(4096) b) { // CHECK: %a.addr.ascast = addrspacecast ptr %a.addr to ptr addrspace(4) // CHECK: %b.addr.ascast = addrspacecast ptr %b.addr to ptr addrspace(4)