[SYCL] Resolve test failures

This is a cherry-pick of #17436 with slight modifications to
`regcall-cc-test.cpp` to make it pass

Patch-By: premanandrao <[email protected]>

Author: premanandrao

clang/lib/CodeGen/CGExprScalar.cpp

@@ -2337,10 +2337,12 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) {
     llvm::Type *DstTy = ConvertType(DestTy);
 
     if (SrcTy->isPointerTy() && DstTy->isPointerTy() &&
-        SrcTy->getPointerAddressSpace() != DstTy->getPointerAddressSpace())
+        SrcTy->getPointerAddressSpace() != DstTy->getPointerAddressSpace()) {
       Src = Builder.CreateAddrSpaceCast(
           Src,
           llvm::PointerType::get(VMContext, DstTy->getPointerAddressSpace()));
+      SrcTy = Src->getType();
+    }
 
     // FIXME: this is a gross but seemingly necessary workaround for an issue
     // manifesting when a target uses a non-default AS for indirect sret args,

clang/test/CodeGenSYCL/address-space-cond-op.cpp

@@ -25,7 +25,7 @@ struct S {
 // CHECK-NEXT:    br label [[COND_END]]
 // CHECK:       cond.end:
 // CHECK-NEXT:    [[COND_LVALUE:%.*]] = phi ptr addrspace(4) [ [[TMP1]], [[COND_TRUE]] ], [ [[RHS_ASCAST]], [[COND_FALSE]] ]
-// CHECK-NEXT:    call void @llvm.memcpy.p4.p4.i64(ptr addrspace(4) align 2 [[AGG_RESULT:%.*]], ptr addrspace(4) align 2 [[COND_LVALUE]], i64 2, i1 false)
+// CHECK-NEXT:    call void @llvm.memcpy.p0.p4.i64(ptr align 2 [[AGG_RESULT:%.*]], ptr addrspace(4) align 2 [[COND_LVALUE]], i64 2, i1 false)
 // CHECK-NEXT:    ret void
 //
 S foo(bool cond, S &lhs, S rhs) {

clang/test/CodeGenSYCL/address-space-of-returns.cpp

@@ -25,7 +25,7 @@ A ret_agg() {
   A a;
   return a;
 }
-// CHECK: define {{.*}}spir_func void @{{.*}}ret_agg{{.*}}(ptr addrspace(4) dead_on_unwind noalias writable sret(%struct{{.*}}.A) align 4 %agg.result)
+// CHECK: define {{.*}}spir_func void @{{.*}}ret_agg{{.*}}(ptr dead_on_unwind noalias writable sret(%struct{{.*}}.A) align 4 %agg.result)
 
 template <typename name, typename Func>
 __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) {

clang/test/CodeGenSYCL/nvptx-short-ptr.cpp

@@ -20,9 +20,9 @@
 
 // Targeting a 32-bit NVPTX, check that we see universal 32-bit pointers (the
 // option changes nothing)
-// CHECK32: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+// CHECK32: target datalayout = "e-p:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
 
 // Targeting a 64-bit NVPTX target, check that we see 32-bit pointers for
 // shared (3), const (4), and local (5) address spaces only.
-// CHECK64-DEFAULT: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
-// CHECK64-SHORT: target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+// CHECK64-DEFAULT: target datalayout = "e-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
+// CHECK64-SHORT: target datalayout = "e-p3:32:32-p4:32:32-p5:32:32-p6:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"

clang/test/CodeGenSYCL/sycl-intelfpga-bitint.cpp

@@ -7,7 +7,7 @@
 
 #include "Inputs/sycl.hpp"
 
-// CHECK: define{{.*}} void @_Z3fooDB4096_S_(ptr addrspace(4) {{.*}} sret(i4096) align 8 %agg.result, ptr {{.*}} byval(i4096) align 8 %[[ARG1:[0-9]+]], ptr {{.*}} byval(i4096) align 8 %[[ARG2:[0-9]+]])
+// CHECK: define{{.*}} void @_Z3fooDB4096_S_(ptr {{.*}} sret(i4096) align 8 %agg.result, ptr {{.*}} byval(i4096) align 8 %[[ARG1:[0-9]+]], ptr {{.*}} byval(i4096) align 8 %[[ARG2:[0-9]+]])
 signed _BitInt(4096) foo(signed _BitInt(4096) a, signed _BitInt(4096) b) {
   // CHECK: %a.addr.ascast = addrspacecast ptr %a.addr to ptr addrspace(4)
   // CHECK: %b.addr.ascast = addrspacecast ptr %b.addr to ptr addrspace(4)