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baderbader
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Merge branch 'sycl' into env_var_update
2 parents 48c5e44 + 5949228 commit cc12e88

35 files changed

+1092
-722
lines changed

‎clang/include/clang/Basic/Attr.td‎

Lines changed: 46 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1217,7 +1217,8 @@ def SYCLIntelKernelArgsRestrict : InheritableAttr {
12171217
}
12181218

12191219
def SYCLIntelNumSimdWorkItems : InheritableAttr {
1220-
let Spellings = [CXX11<"intelfpga","num_simd_work_items">];
1220+
let Spellings = [CXX11<"intelfpga","num_simd_work_items">,
1221+
CXX11<"intel","num_simd_work_items">];
12211222
let Args = [ExprArgument<"Value">];
12221223
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12231224
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1244,7 +1245,8 @@ def SYCLIntelSchedulerTargetFmaxMhz : InheritableAttr {
12441245
}
12451246

12461247
def SYCLIntelMaxWorkGroupSize : InheritableAttr {
1247-
let Spellings = [CXX11<"intelfpga","max_work_group_size">];
1248+
let Spellings = [CXX11<"intelfpga","max_work_group_size">,
1249+
CXX11<"intel","max_work_group_size">];
12481250
let Args = [UnsignedArgument<"XDim">,
12491251
UnsignedArgument<"YDim">,
12501252
UnsignedArgument<"ZDim">];
@@ -1255,7 +1257,8 @@ def SYCLIntelMaxWorkGroupSize : InheritableAttr {
12551257
}
12561258

12571259
def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
1258-
let Spellings = [CXX11<"intelfpga","max_global_work_dim">];
1260+
let Spellings = [CXX11<"intelfpga","max_global_work_dim">,
1261+
CXX11<"intel","max_global_work_dim">];
12591262
let Args = [UnsignedArgument<"Number">];
12601263
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12611264
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1264,7 +1267,8 @@ def SYCLIntelMaxGlobalWorkDim : InheritableAttr {
12641267
}
12651268

12661269
def SYCLIntelNoGlobalWorkOffset : InheritableAttr {
1267-
let Spellings = [CXX11<"intelfpga","no_global_work_offset">];
1270+
let Spellings = [CXX11<"intelfpga","no_global_work_offset">,
1271+
CXX11<"intel","no_global_work_offset">];
12681272
let Args = [BoolArgument<"Enabled", 1>];
12691273
let LangOpts = [SYCLIsDevice, SYCLIsHost];
12701274
let Subjects = SubjectList<[Function], ErrorDiag>;
@@ -1717,7 +1721,8 @@ def Mode : Attr {
17171721
}
17181722

17191723
def SYCLIntelFPGAIVDep : Attr {
1720-
let Spellings = [CXX11<"intelfpga","ivdep">];
1724+
let Spellings = [CXX11<"intelfpga","ivdep">,
1725+
CXX11<"intel","ivdep">];
17211726
let Args = [
17221727
ExprArgument<"SafelenExpr">, ExprArgument<"ArrayExpr">,
17231728
UnsignedArgument<"SafelenValue">
@@ -1763,7 +1768,8 @@ def SYCLIntelFPGAIVDep : Attr {
17631768
}
17641769

17651770
def SYCLIntelFPGAII : Attr {
1766-
let Spellings = [CXX11<"intelfpga","ii">];
1771+
let Spellings = [CXX11<"intelfpga","ii">,
1772+
CXX11<"intel","ii">];
17671773
let Args = [ExprArgument<"IntervalExpr">];
17681774
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17691775
let HasCustomTypeTransform = 1;
@@ -1776,7 +1782,8 @@ def SYCLIntelFPGAII : Attr {
17761782
}
17771783

17781784
def SYCLIntelFPGAMaxConcurrency : Attr {
1779-
let Spellings = [CXX11<"intelfpga","max_concurrency">];
1785+
let Spellings = [CXX11<"intelfpga","max_concurrency">,
1786+
CXX11<"intel","max_concurrency">];
17801787
let Args = [ExprArgument<"NThreadsExpr">];
17811788
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17821789
let HasCustomTypeTransform = 1;
@@ -1789,7 +1796,8 @@ def SYCLIntelFPGAMaxConcurrency : Attr {
17891796
}
17901797

17911798
def SYCLIntelFPGALoopCoalesce : Attr {
1792-
let Spellings = [CXX11<"intelfpga","loop_coalesce">];
1799+
let Spellings = [CXX11<"intelfpga","loop_coalesce">,
1800+
CXX11<"intel","loop_coalesce">];
17931801
let Args = [ExprArgument<"NExpr">];
17941802
let LangOpts = [SYCLIsDevice, SYCLIsHost];
17951803
let HasCustomTypeTransform = 1;
@@ -1802,7 +1810,8 @@ def SYCLIntelFPGALoopCoalesce : Attr {
18021810
}
18031811

18041812
def SYCLIntelFPGADisableLoopPipelining : Attr {
1805-
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">];
1813+
let Spellings = [CXX11<"intelfpga","disable_loop_pipelining">,
1814+
CXX11<"intel","disable_loop_pipelining">];
18061815
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18071816
let HasCustomTypeTransform = 1;
18081817
let AdditionalMembers = [{
@@ -1814,7 +1823,8 @@ def SYCLIntelFPGADisableLoopPipelining : Attr {
18141823
}
18151824

18161825
def SYCLIntelFPGAMaxInterleaving : Attr {
1817-
let Spellings = [CXX11<"intelfpga","max_interleaving">];
1826+
let Spellings = [CXX11<"intelfpga","max_interleaving">,
1827+
CXX11<"intel","max_interleaving">];
18181828
let Args = [ExprArgument<"NExpr">];
18191829
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18201830
let HasCustomTypeTransform = 1;
@@ -1827,7 +1837,8 @@ def SYCLIntelFPGAMaxInterleaving : Attr {
18271837
}
18281838

18291839
def SYCLIntelFPGASpeculatedIterations : Attr {
1830-
let Spellings = [CXX11<"intelfpga","speculated_iterations">];
1840+
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
1841+
CXX11<"intel","speculated_iterations">];
18311842
let Args = [ExprArgument<"NExpr">];
18321843
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18331844
let HasCustomTypeTransform = 1;
@@ -1872,23 +1883,26 @@ def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
18721883
"local variables, static variables">;
18731884

18741885
def IntelFPGADoublePump : Attr {
1875-
let Spellings = [CXX11<"intelfpga", "doublepump">];
1886+
let Spellings = [CXX11<"intelfpga", "doublepump">,
1887+
CXX11<"intel", "doublepump">];
18761888
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
18771889
Field], ErrorDiag>;
18781890
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18791891
let Documentation = [IntelFPGADoublePumpAttrDocs];
18801892
}
18811893

18821894
def IntelFPGASinglePump : Attr {
1883-
let Spellings = [CXX11<"intelfpga", "singlepump">];
1895+
let Spellings = [CXX11<"intelfpga", "singlepump">,
1896+
CXX11<"intel", "singlepump">];
18841897
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
18851898
Field], ErrorDiag>;
18861899
let LangOpts = [SYCLIsDevice, SYCLIsHost];
18871900
let Documentation = [IntelFPGASinglePumpAttrDocs];
18881901
}
18891902

18901903
def IntelFPGAMemory : Attr {
1891-
let Spellings = [CXX11<"intelfpga", "memory">];
1904+
let Spellings = [CXX11<"intelfpga", "memory">,
1905+
CXX11<"intel", "fpga_memory">];
18921906
let Args = [EnumArgument<"Kind", "MemoryKind",
18931907
["MLAB", "BLOCK_RAM", ""],
18941908
["MLAB", "BlockRAM", "Default"], 1>];
@@ -1908,7 +1922,8 @@ def IntelFPGAMemory : Attr {
19081922
}
19091923

19101924
def IntelFPGARegister : Attr {
1911-
let Spellings = [CXX11<"intelfpga", "register">];
1925+
let Spellings = [CXX11<"intelfpga", "register">,
1926+
CXX11<"intel", "fpga_register">];
19121927
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19131928
Field], ErrorDiag>;
19141929
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -1917,7 +1932,8 @@ def IntelFPGARegister : Attr {
19171932

19181933
// One integral argument.
19191934
def IntelFPGABankWidth : Attr {
1920-
let Spellings = [CXX11<"intelfpga","bankwidth">];
1935+
let Spellings = [CXX11<"intelfpga","bankwidth">,
1936+
CXX11<"intel","bankwidth">];
19211937
let Args = [ExprArgument<"Value">];
19221938
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19231939
Field], ErrorDiag>;
@@ -1934,7 +1950,8 @@ def IntelFPGABankWidth : Attr {
19341950
}
19351951

19361952
def IntelFPGANumBanks : Attr {
1937-
let Spellings = [CXX11<"intelfpga","numbanks">];
1953+
let Spellings = [CXX11<"intelfpga","numbanks">,
1954+
CXX11<"intel","numbanks">];
19381955
let Args = [ExprArgument<"Value">];
19391956
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19401957
Field], ErrorDiag>;
@@ -1951,7 +1968,8 @@ def IntelFPGANumBanks : Attr {
19511968
}
19521969

19531970
def IntelFPGAPrivateCopies : InheritableAttr {
1954-
let Spellings = [CXX11<"intelfpga","private_copies">];
1971+
let Spellings = [CXX11<"intelfpga","private_copies">,
1972+
CXX11<"intel","private_copies">];
19551973
let Args = [ExprArgument<"Value">];
19561974
let LangOpts = [SYCLIsDevice, SYCLIsHost];
19571975
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
@@ -1968,7 +1986,8 @@ def IntelFPGAPrivateCopies : InheritableAttr {
19681986

19691987
// Two string arguments.
19701988
def IntelFPGAMerge : Attr {
1971-
let Spellings = [CXX11<"intelfpga","merge">];
1989+
let Spellings = [CXX11<"intelfpga","merge">,
1990+
CXX11<"intel","merge">];
19721991
let Args = [StringArgument<"Name">, StringArgument<"Direction">];
19731992
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalOrStaticVar,
19741993
Field], ErrorDiag>;
@@ -1977,7 +1996,8 @@ def IntelFPGAMerge : Attr {
19771996
}
19781997

19791998
def IntelFPGAMaxReplicates : Attr {
1980-
let Spellings = [CXX11<"intelfpga","max_replicates">];
1999+
let Spellings = [CXX11<"intelfpga","max_replicates">,
2000+
CXX11<"intel","max_replicates">];
19812001
let Args = [ExprArgument<"Value">];
19822002
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19832003
Field], ErrorDiag>;
@@ -1994,7 +2014,8 @@ def IntelFPGAMaxReplicates : Attr {
19942014
}
19952015

19962016
def IntelFPGASimpleDualPort : Attr {
1997-
let Spellings = [CXX11<"intelfpga","simple_dual_port">];
2017+
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
2018+
CXX11<"intel","simple_dual_port">];
19982019
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
19992020
Field], ErrorDiag>;
20002021
let LangOpts = [SYCLIsDevice, SYCLIsHost];
@@ -2019,7 +2040,8 @@ def SYCLIntelPipeIO : Attr {
20192040

20202041
// Variadic integral arguments.
20212042
def IntelFPGABankBits : Attr {
2022-
let Spellings = [CXX11<"intelfpga", "bank_bits">];
2043+
let Spellings = [CXX11<"intelfpga", "bank_bits">,
2044+
CXX11<"intel", "bank_bits">];
20232045
let Args = [VariadicExprArgument<"Args">];
20242046
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20252047
Field], ErrorDiag>;
@@ -2036,7 +2058,8 @@ def IntelFPGABankBits : Attr {
20362058
}
20372059

20382060
def IntelFPGAForcePow2Depth : Attr {
2039-
let Spellings = [CXX11<"intelfpga","force_pow2_depth">];
2061+
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
2062+
CXX11<"intel","force_pow2_depth">];
20402063
let Args = [ExprArgument<"Value">];
20412064
let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar,
20422065
Field], ErrorDiag>;

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