From 93eacfffd77f7ca022422535f2efb1d05d56ec20 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Sat, 2 May 2015 16:27:38 +0800 Subject: [PATCH 1/3] clk: hi6220: add rtc clk Signed-off-by: Zhangfei Gao --- drivers/clk/hisilicon/clk-hi6220.c | 2 ++ include/dt-bindings/clock/hi6220-clock.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c index 2698a4ce2cd333..4ea7e975f2b2bd 100644 --- a/drivers/clk/hisilicon/clk-hi6220.c +++ b/drivers/clk/hisilicon/clk-hi6220.c @@ -69,6 +69,8 @@ static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = { { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, }, { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, }, { HI6220_UART0_PCLK, "uart0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, }, + { HI6220_RTC0_PCLK, "rtc0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, }, + { HI6220_RTC1_PCLK, "rtc1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, }, }; static struct hisi_clock_data *clk_data_ao; diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h index 563c9b9936ad71..d245393df00c08 100644 --- a/include/dt-bindings/clock/hi6220-clock.h +++ b/include/dt-bindings/clock/hi6220-clock.h @@ -55,6 +55,8 @@ #define HI6220_TIMER7_PCLK 38 #define HI6220_TIMER8_PCLK 39 #define HI6220_UART0_PCLK 40 +#define HI6220_RTC0_PCLK 41 +#define HI6220_RTC1_PCLK 42 #define HI6220_AO_NR_CLKS 48 From bae9a611fd15b931b31aca41c679b4838abc5637 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Sat, 2 May 2015 16:28:18 +0800 Subject: [PATCH 2/3] dts: hi6220: add rtc0 Signed-off-by: Zhangfei Gao --- arch/arm64/boot/dts/hi6220.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/hi6220.dtsi b/arch/arm64/boot/dts/hi6220.dtsi index 47e755e8ae12e3..064bef68a748b4 100644 --- a/arch/arm64/boot/dts/hi6220.dtsi +++ b/arch/arm64/boot/dts/hi6220.dtsi @@ -286,6 +286,14 @@ status = "disabled"; }; + rtc0: rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x0 0xf8003000 0x0 0x1000>; + interrupts = <0 12 4>; + clocks = <&clock_ao HI6220_RTC0_PCLK>; + clock-names = "apb_pclk"; + }; + dma0: dma@f7370000 { compatible = "hisilicon,k3-dma-1.0"; reg = <0x0 0xf7370000 0x0 0x1000>; From 7539ccced1baab78586ed06e99eca7c67d6ff015 Mon Sep 17 00:00:00 2001 From: Zhangfei Gao Date: Sat, 2 May 2015 16:28:44 +0800 Subject: [PATCH 3/3] defconfig: enable CONFIG_RTC_DRV_PL031 Signed-off-by: Zhangfei Gao --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 97e2049baa75e5..8c11b501c0d825 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -316,6 +316,7 @@ CONFIG_LEDS_TRIGGER_CPU=y CONFIG_SWITCH=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_PL031=y CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y CONFIG_HISI300_EDMAC=y