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vt100.qsf
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vt100.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 22:17:10 August 05, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# vt100_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5T144C8
set_global_assignment -name TOP_LEVEL_ENTITY vt100
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:17:10 AUGUST 05, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name VHDL_FILE ps2_keyboard.vhd
set_global_assignment -name VHDL_FILE debounce.vhd
set_global_assignment -name VHDL_FILE sram.vhd
set_global_assignment -name VHDL_FILE font_rom.vhd
set_global_assignment -name VHDL_FILE displayram.vhd
set_global_assignment -name VHDL_FILE bootrom.vhd
set_global_assignment -name VHDL_FILE components/T16450.vhd
set_global_assignment -name VHDL_FILE components/T80s.vhd
set_global_assignment -name VHDL_FILE components/T80a.vhd
set_global_assignment -name VHDL_FILE components/T80_Reg.vhd
set_global_assignment -name VHDL_FILE components/T80_Pack.vhd
set_global_assignment -name VHDL_FILE components/T80_MCode.vhd
set_global_assignment -name VHDL_FILE components/T80_ALU.vhd
set_global_assignment -name VHDL_FILE components/T80.vhd
set_global_assignment -name HEX_FILE "VGA-ROM-8x16.hex"
set_global_assignment -name VHDL_FILE "vga-controller.vhd"
set_global_assignment -name VHDL_FILE "colour-rom.vhd"
set_global_assignment -name VHDL_FILE simulation/modelsim/testbench.vhd
set_global_assignment -name VHDL_FILE vt100.vhd
set_global_assignment -name VHDL_FILE simulation/modelsim/vga_testbench.vhd
set_global_assignment -name VHDL_FILE vga_textmode.vhd
set_global_assignment -name QIP_FILE font_rom.qip
set_global_assignment -name VHDL_FILE simulation/modelsim/vga_gfx_testbench.vhd
set_global_assignment -name VHDL_FILE "vga-small.vhd"
set_global_assignment -name QIP_FILE displayram.qip
set_global_assignment -name QIP_FILE bootrom.qip
set_global_assignment -name QIP_FILE sram.qip
set_global_assignment -name SDC_FILE vt100.sdc
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
set_location_assignment PIN_31 -to blinkenlight[0]
set_location_assignment PIN_25 -to blinkenlight[1]
set_location_assignment PIN_30 -to blinkenlight[2]
set_location_assignment PIN_28 -to blinkenlight[3]
set_location_assignment PIN_24 -to blinkenlight[4]
set_location_assignment PIN_32 -to blinkenlight[5]
set_location_assignment PIN_112 -to hSync
set_location_assignment PIN_113 -to vSync
set_location_assignment PIN_126 -to videoR[0]
set_location_assignment PIN_132 -to videoR[1]
set_location_assignment PIN_134 -to videoR[2]
set_location_assignment PIN_136 -to videoR[3]
set_location_assignment PIN_125 -to videoG[0]
set_location_assignment PIN_121 -to videoG[1]
set_location_assignment PIN_119 -to videoG[2]
set_location_assignment PIN_115 -to videoG[3]
set_location_assignment PIN_122 -to videoB[0]
set_location_assignment PIN_120 -to videoB[1]
set_location_assignment PIN_118 -to videoB[2]
set_location_assignment PIN_114 -to videoB[3]
set_parameter -name CYCLONEII_SAFE_WRITE VERIFIED_SAFE
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top