diff --git a/dag/extdeps/cpu_attachment/ilm4926.dag b/dag/extdeps/cpu_attachment/ilm4926.dag index 2b818638aa2..df69d45921d 100644 --- a/dag/extdeps/cpu_attachment/ilm4926.dag +++ b/dag/extdeps/cpu_attachment/ilm4926.dag @@ -10,6 +10,7 @@ import extdeps.cpu.ampere { import extdeps.ocp.mt_jade.subject { mt_jade_subject_authority_anchor } import extdeps.vendor.ampere { ampere_customer_reference_boards_authority } import extdeps.vendor.lotes { lotes } +import extdeps.cpu_attachment.lotes_azifa072 { azifa072_drawing_authority, azifa072_footprint_may_emit } import extdeps.vendor { Vendor } import extdeps.hardware { Hardware } import extdeps.uri { Uri, Https } @@ -235,7 +236,13 @@ data lotes_azif0222_catalogue_note: String = "Lotes catalogue page for ARM P/N A // THE SOCKET BODY IS A SEPARATE, UNNAMED PART, and this row exists so that resolving the // retention assembly cannot be mistaken for resolving the attachment. It is the layer that // carries the board land pattern. -data socket_body_part_is_unnamed_note: String = "No consulted source names an orderable socket-body part for LGA4926. Lotes AZIF0222 is the ILM and backplate assembly; the socket body that receives the processor and solders to the board is a different item. Resolving it is what would make the board land pattern obtainable." +// RESOLVED 2026-08-23, AND THE SENTENCE THIS REPLACES IS DELETED RATHER THAN ANNOTATED. It read +// that no consulted source names an orderable socket-body part; that became false the moment the +// drawing arrived, and a knowingly-false claim standing beside its own correction is two accounts +// of one fact. What the old row got RIGHT is preserved: the socket body is a different item from +// AZIF0222, and resolving it is what made the land pattern obtainable. That is exactly what +// happened, by exactly the route lga4926_land_pattern_public_route predicted. +data socket_body_part_resolution_note: String = "Lotes supplied AZIFA072-P001CCS, drawing GAP-AZIFA072 rev 2, in direct response to the request recorded in lga4926_land_pattern_public_route: the socket-body part that mates with AZIF0222, with its customer drawing and the board land pattern. The part, its geometry and its remaining gaps are modelled in extdeps.cpu_attachment.lotes_azifa072. The public route resolved and the access-gated route was never taken, so the geometry is carriable rather than merely known." // THE MECHANICAL DRAWING THE SAME THREAD CARRIES, AND WHAT IT IS NOT. A dimensioned plan view of // the retention frame was posted alongside the part numbers: a bezel with a central opening, a cam @@ -346,13 +353,51 @@ fn attachment_socket_body_is_identified(a: AttachmentStanding) -> Bool { } // A FOOTPRINT MAY NOT EMIT WHILE THE SOCKET BODY IS UNIDENTIFIED. The land pattern belongs to a -// part, so a released footprint whose part is unknown is a drawing of nothing -- this is the -// predicate a footprint emitter consults, not a comment asking it to be careful. +// part, so a released footprint whose part is unknown is a drawing of nothing. +// +// THE RUNG, STATED RATHER THAN IMPLIED (corrected 2026-08-23): an earlier revision of this comment +// called this "the predicate a footprint emitter consults, not a comment asking it to be careful". +// No footprint emitter exists in the tree -- measured, not assumed: the only consumers of this +// function are the witnesses. So the sentence claimed enforcement the corpus does not have, which +// is the specification-without-execution failure wearing the vocabulary of a wall. The predicate +// itself is real and executes correctly; what is absent is anything that must ask it. +// NEXT-RUNG TRIGGER: the first caller in product.pcb.footprint that turns a land pattern into pads. +// +// THE THIRD CONJUNCT WAS ADDED BECAUSE THE FIRST TWO WENT TRUE AND THE FOOTPRINT STILL WAS NOT +// RELEASABLE (2026-08-23). When the Lotes drawing resolved the socket body, this gate flipped +// from refusing to permitting on the same run that added it -- measured, not reasoned about -- +// while the stencil aperture was unread, the Pin 1 corner unlocated and the mask opening +// unidentified. That is the gate failing open at the exact moment it was supposed to start +// working, and the mechanism is worth naming: ESTABLISHED IS NOT COMPLETE. The board land +// pattern IS established -- count, pitch, diameter and every position are cited to a publisher +// of record -- so no honest edit to the standing rows would have caught this. Establishment is +// a property of a FACT's grounding; releasability is a property of a DELIVERABLE's completeness, +// and a gate that reads only the first will always permit as soon as the last citation lands. +// +// The conjunct names the LGA4926 socket body specifically, which is correct rather than a leak: +// this module is the LGA4926 designation, not a generic attachment shape, so the part that +// carries this designation's land pattern is the same subject and not a foreign one. fn attachment_footprint_may_emit(a: AttachmentStanding) -> Bool { attachment_socket_body_is_identified(a: a) && standing_is_established(s: attachment_board_land_pattern(a: a)) } +// THE RELEASE GATE FOR THIS ACTUAL PART, WHICH IS A DIFFERENT QUESTION AND THEREFORE A DIFFERENT +// FUNCTION. An earlier revision of this diff conjoined the socket body's open gaps directly into +// attachment_footprint_may_emit above, and running the witnesses is what showed why that is +// wrong: the gaps are a fact about ONE part, so folding them into a predicate over an arbitrary +// AttachmentStanding made that predicate false for EVERY input including its own synthetic +// positive control. A gate no input can turn green is not a strict gate, it is a decoration -- +// permanently red by construction, carrying no information (DESIGN section 4b). +// +// So the two questions are separated: does a standing describe an identified socket body with an +// established land pattern (above, flippable, and its RED and GREEN controls stay authorable), +// and may the LGA4926 footprint be released today (here, and it may not). +fn lga4926_footprint_may_release() -> Bool { + attachment_footprint_may_emit(a: ilm4926_attachment_standing) + && azifa072_footprint_may_emit() +} + fn attachment_unresolved_constituent_count(a: AttachmentStanding) -> Int { let socket_unresolved = if attachment_socket_body_is_identified(a: a) { 0 } else { 1 } let retention_unresolved = if standing_is_established(s: a.retention_assembly.orderable_part_number) { 0 } else { 1 } @@ -399,17 +444,17 @@ fn route_yields_a_carriable_fact(r: LandPatternRoute) -> Bool { data ilm4926_attachment_standing: AttachmentStanding = AttachmentStanding { socket_body: SocketBodyStanding { - vendor_identity: DesignationFactUnresolved { - reason: "no publisher of record attributes the socket body to a manufacturer. Ampere and OCP name the designator ILM4926 only, and Lotes publishes the retention assembly without naming what it mates with. Lotes is the strongest lead precisely because it manufactures the retention assembly for this designation and manufactures LGA socket bodies generally, including for AMD Socket AM5 -- but manufacturing one constituent is not attribution of another.", - next_authority_to_consult: Present { value: lotes_azif0222_product_authority }, + vendor_identity: DesignationFactEstablished { + value: "Lotes Co., Ltd", + authority: azifa072_drawing_authority, }, - orderable_part_number: DesignationFactUnresolved { - reason: "no source names an orderable socket-body part for LGA4926. AZIF0222 is the retention assembly and is recorded there; it is not the item that receives the processor and solders to the board. Public retail search found no socket-body listing either, which is an observation about distribution rather than evidence the part has no number -- a low-volume server socket sold direct to board makers would not appear in retail regardless.", - next_authority_to_consult: Present { value: lotes_azif0222_product_authority }, + orderable_part_number: DesignationFactEstablished { + value: "AZIFA072-P001CCS, drawing GAP-AZIFA072 rev 2, title LGA4926 SOCKET -- the socket body that receives the processor and solders to the board, distinct from the AZIF0222 retention assembly", + authority: azifa072_drawing_authority, }, - board_land_pattern: DesignationFactUnresolved { - reason: "the board-side land pattern is stated in no public document consulted. The Altra Platform Hardware Design Specification does name a document titled Altra PCB Layout Guidelines on Ampere Customer Connect, at sections 4.2.2 and 4.3.2 — but both of those sections are titled Reference Layout and sit under 4.2 VRD Implementation using Texas Instruments Devices and 4.3 VRD Implementation using Infineon Devices, so what they route to is voltage-regulator layout. That the named document ALSO carries the processor socket land pattern is unverified: its title is general enough to permit it, its contents are access-gated, and a pointer read out of a voltage-regulator section establishes what a document is named, never what it holds. A SECOND and independent route exists and is carried separately in lga4926_land_pattern_public_route, because one next-authority field cannot hold two routes whose carriage consequences differ.", - next_authority_to_consult: Present { value: ampere_customer_reference_boards_authority }, + board_land_pattern: DesignationFactEstablished { + value: "4926 pads, Ø0.46 +/-0.05 mm, staggered lattice at 1.000 mm column pitch and 0.870 mm row pitch, array extent 63.449 x 75.470 mm; positions and outline carried in extdeps.cpu_attachment.lotes_azifa072. NOT a complete footprint release: that module's azifa072_open_gaps still carries the stencil aperture, the Pin 1 corner and the mask opening, and azifa072_footprint_may_emit refuses while they stand.", + authority: azifa072_drawing_authority, }, }, retention_assembly: ConstituentStanding { diff --git a/dag/extdeps/cpu_attachment/lotes_azifa072.dag b/dag/extdeps/cpu_attachment/lotes_azifa072.dag new file mode 100644 index 00000000000..5955c4f1e99 --- /dev/null +++ b/dag/extdeps/cpu_attachment/lotes_azifa072.dag @@ -0,0 +1,343 @@ +module extdeps.cpu_attachment.lotes_azifa072 + +import std.types { Bool, List, NonEmptyStr } +import std.integer { Int } +import std.decl_ref { DeclarationRef, WholeDeclaration } +import extdeps.external_authority { ExternalAuthority, ExternalModelScope, ExternalSubjectRef } +import extdeps.uri { Uri, File, Https } +import extdeps.vendor.lotes { lotes } +import extdeps.vendor { Vendor } +import extdeps.hardware { Hardware } + +// THE SOCKET BODY, WHICH IS A DIFFERENT PART FROM THE RETENTION ASSEMBLY AND HAS ITS OWN +// AUTHORITY. extdeps.cpu_attachment.ilm4926 carries the DESIGNATION -- what ILM4926 names, and +// how strongly each publisher attests it -- and resolved one constituent, the ILM-and-backplate +// assembly AZIF0222. This module is a second, independently versioned Lotes product: the item +// that receives the processor and solders to the board. Two orderable parts from one vendor are +// two subjects, not one (DESIGN section 3, external upstream decomposition), so a revision of +// this drawing must not require editing the designation module. +// +// WHY IT LANDS HERE RATHER THAN INSIDE ilm4926: that module's whole content is a designation +// whose referent no cited document fixed. Folding a resolved part into it would make the +// unresolved-referent question look answered by the part's arrival, and it is not -- what the +// four-letter designator EXPANDS to is still unattested. A part number resolves procurement; it +// does not retroactively expand an initialism. +// THE AUTHORITY IS THE ROUTE TO THE DRAWING, NOT A COPY OF IT (corrected 2026-08-23). An earlier +// revision of this module cited a File URI pointing at the vendor's PDF committed into this +// repository. That is refused by repository policy for EVERY subject, not as a per-subject +// judgement: product.altra_motherboard.attachment_stack states it on RepositoryCarriageStanding, +// where the deliberately absent fourth arm is SourceExpressionMayBeCarried, because copying a +// vendor's PDF, figure, prose or table layout is never a degree of freedom a row may grant itself. +// The operator's clearance covered CONFIDENTIALITY -- there is no NDA on this part -- which is a +// different question from whether this repository carries a vendor's expression of its own facts. +// Both had to be true and only the first was checked. +// +// So the drawing is cited the way this repository already cites every document it does not hold: +// by the route through which it can be obtained, with the document's exact identity carried +// beside it in azifa072_drawing. That is the same shape as extdeps.vendor.ampere's Customer +// Connect anchor -- a locator for the route, not for the bytes. A later reader resolves this +// citation by asking Lotes for GAP-AZIFA072 revision 2, which is precisely how it was obtained. +data azifa072_drawing_authority: ExternalAuthority = ExternalAuthority { + uri: Uri { + scheme: Https + locator: "www.lotes.cc/en/contact.php" + } +} + +// THE ANCHOR IS A BINDING, NOT A SECOND URI. extdeps.cpu_attachment.ilm4926 does the same thing +// with the Ampere datasheet locators: the conventional anchor name points at the declaration that +// already holds the authority, so the locator is typed once and a consumer that wants to name the +// drawing specifically has a name for it that does not collide across modules. +data extdeps_external_authority_anchor: ExternalAuthority = azifa072_drawing_authority + +// THE DRAWING IS COMMITTED, AND THAT IS WHY THE CITATION IS A FILE URI. It arrived by direct +// vendor correspondence rather than from a catalogue page, so there is no public locator to +// point at; a citation naming a document only this repository's authors have seen is not a +// citation. Committing the bytes is what makes the reference resolvable by a later reader, and +// the absence of any confidentiality marking is what makes committing them permissible. +// CARRIABILITY IS A TYPED FACT, NOT A REASSURING SENTENCE. Whether a document's content may be +// reproduced in a public repository decides whether resolving a question ADVANCES the model or +// merely satisfies a reader, and ilm4926 already types that distinction on its two routes +// (route_yields_a_carriable_fact). Writing it as prose here would leave the one fact that governs +// what may be copied out of this drawing invisible to everything except a human re-reading it. +type DocumentCarriage + = CarriableOpenSupply { + supplied_in_response_to: NonEmptyStr + no_confidentiality_marking_observed: Bool + } + | NotCarriableAccessGated { gate: NonEmptyStr } + +// THE SECOND FIELD IS AN OBSERVATION, AND ITS NAME SAYS SO. "No confidentiality marking observed" +// is what this repository checked; it is not a legal clearance and must not read as one. The arm +// is still Carriable because the operator cleared it in the request that produced this work -- +// the observation supports that ruling rather than substituting for it. +data azifa072_drawing_carriage: DocumentCarriage = CarriableOpenSupply { + supplied_in_response_to: "the socket-body part number that mates with AZIF0222, then its customer drawing or recommended PCB layout -- the public route recorded in extdeps.cpu_attachment.ilm4926 lga4926_land_pattern_public_route", + no_confidentiality_marking_observed: true, +} + +fn document_content_may_be_carried(c: DocumentCarriage) -> Bool { + match c { + CarriableOpenSupply { supplied_in_response_to: _, no_confidentiality_marking_observed: seen } => seen + NotCarriableAccessGated { gate: _ } => false + } +} + +data lotes_catalogue_authority: ExternalAuthority = ExternalAuthority { + uri: Uri { + scheme: Https + locator: "www.lotes.cc/en/about.php" + } +} + +// DOCUMENT IDENTITY IS CARRIED, NOT SUMMARISED. A drawing is only an authority for the revision +// it is; a geometry fact read off revision 2 is not a fact about revision 3, and a reader who +// finds a newer PDF needs enough here to tell whether this module's numbers still stand. +type CustomerDrawing { + drawing_number: NonEmptyStr + part_number: NonEmptyStr + title: NonEmptyStr + revision: NonEmptyStr + engineering_change_notice: NonEmptyStr + sheet_count: Int + authority: ExternalAuthority +} + +data azifa072_drawing: CustomerDrawing = CustomerDrawing { + drawing_number: "GAP-AZIFA072", + part_number: "AZIFA072-P001CCS", + title: "LGA4926 SOCKET", + revision: "2", + engineering_change_notice: "N230045, 04/10'2023", + sheet_count: 5, + authority: azifa072_drawing_authority, +} + +data azifa072_socket_body_vendor: Vendor = lotes + +data extdeps_model_scope: ExternalModelScope = ExternalModelScope { + subject: ExternalSubjectRef { + declaration: DeclarationRef { + module_path: "extdeps.cpu_attachment.lotes_azifa072", + decl_name: "azifa072_drawing", + field: WholeDeclaration + } + }, + first_citation: azifa072_drawing_authority, + further_citations: [lotes_catalogue_authority] +} + +// ================= THE LAND PATTERN ================= +// +// EVERY FIELD BELOW IS A DRAWING FACT OR A CROSS-CHECKED EXTRACTION, AND THE TWO ARE DIFFERENT +// EPISTEMIC STATES. A callout is what the vendor wrote; an extraction is what this repository +// measured off the vector content. They are separated because their failure modes differ -- a +// callout can be misread, an extraction can be mis-scaled -- and because a reader deciding +// whether to trust a number needs to know which kind it is. Where both exist and agree, that +// agreement is itself recorded rather than collapsed into one unlabelled number. +type GeometryProvenance + = VendorCallout { sheet: Int, wording: NonEmptyStr } + | ExtractedFromDrawingVectors { method: NonEmptyStr } + | CalloutConfirmedByExtraction { sheet: Int, wording: NonEmptyStr, agreement: NonEmptyStr } + +// THE LATTICE IS CARRIED AS PARAMETERS, NOT AS 4,926 ROWS. The array is generated by a staggered +// lattice with voids; storing every centre in this module would be storing a derivable fact +// 4,926 times (DESIGN section 2). The positions ARE committed, as a CSV beside the drawing, because +// the voids are not derivable from the parameters -- but the CSV is a derived artifact of the +// drawing, not a second authority for the pitch. +type StaggeredLattice { + column_pitch_um: Int + row_pitch_um: Int + row_stagger_um: Int + nearest_neighbour_um: Int +} + +// MICROMETRES, BECAUSE THE PITCH IS EXACT AND A DECIMAL IS NOT. 1.000 mm and 0.870 mm are exact +// vendor quantities; carrying them as Int micrometres makes the exactness structural rather than +// dependent on how a float prints. +data azifa072_lattice: StaggeredLattice = StaggeredLattice { + column_pitch_um: 1000, + row_pitch_um: 870, + row_stagger_um: 500, + nearest_neighbour_um: 1000, +} + +data azifa072_lattice_provenance: GeometryProvenance = ExtractedFromDrawingVectors { + method: "sheet 3 pad view, per-row column-index fit over the drawn pad centres; scale fixed by setting the within-row pitch to 1.000 mm and confirmed independently against the sheet 4 detail circle, which measures 0.4599 mm at its stated 80:1 against a 0.46 callout", +} + +type PadGeometry { + pad_count: Int + pad_diameter_um: Int + pad_diameter_tolerance_um: Int + array_extent_x_um: Int + array_extent_y_um: Int + row_count: Int +} + +data azifa072_pad_geometry: PadGeometry = PadGeometry { + pad_count: 4926, + pad_diameter_um: 460, + pad_diameter_tolerance_um: 50, + array_extent_x_um: 63449, + array_extent_y_um: 75470, + row_count: 84, +} + +data azifa072_pad_count_provenance: GeometryProvenance = CalloutConfirmedByExtraction { + sheet: 3, + wording: "4926 X Ø0.46 ±0.05 PCB PADS", + agreement: "the sheet 3 pad view yields exactly 4926 drawn pad elements after eleven off-block strays are dropped; the callout count and the drawn count were obtained independently and match exactly", +} + +data azifa072_pad_positions_artifact: ExternalAuthority = ExternalAuthority { + uri: Uri { + scheme: File + locator: "docs/extdeps/lotes_azifa072/lga4926_pcb_pads.csv" + } +} + +// THE INTERIOR VOIDS ARE WHY THE CSV EXISTS, AND THE DISCREPANCY IS CARRIED AS NUMBERS RATHER +// THAN AS PROSE. A lattice plus an outline does not reproduce this array, and the size of the +// shortfall is the whole reason the extracted positions are committed as an artifact instead of +// regenerated from azifa072_lattice. Written as a sentence, "359 positions are depopulated" +// is a claim no reader can check and no lens can see; as three fields with a derived identity +// it is arithmetic that either holds or does not (DESIGN section 4c -- a machine-consumed fact +// belongs in a typed carrier, and a String whose sole purpose is commentary is misplaced data). +type LatticeFillDiscrepancy { + outline_fill_position_count: Int + actual_pad_count: Int + depopulated_position_count: Int + bank_count: Int + bank_gap_um: Int + central_void_width_um: Int + central_void_height_um: Int +} + +data azifa072_fill_discrepancy: LatticeFillDiscrepancy = LatticeFillDiscrepancy { + outline_fill_position_count: 5285, + actual_pad_count: 4926, + depopulated_position_count: 359, + bank_count: 2, + bank_gap_um: 4130, + central_void_width_um: 13900, + central_void_height_um: 25000, +} + +// THE THIRD FIELD IS DERIVABLE FROM THE FIRST TWO, AND THAT IS THE POINT. Carrying it and +// checking it is not redundancy: the fill count and the pad count come from DIFFERENT sources -- +// the STEP solid's perimeter and the drawing's own vector content -- so their difference is a +// cross-source arithmetic identity. A future edit that changes one number without the other is +// the failure this catches, and it is decidable rather than a matter of someone re-reading prose. +// THE SUBTRACTION IS PARENTHESISED ON ONE LINE ON PURPOSE, AND THE REASON IS A LANGUAGE DEFECT +// RATHER THAN TASTE. Written across lines with the operator leading its continuation -- +// azifa072_fill_discrepancy.outline_fill_position_count +// - azifa072_fill_discrepancy.actual_pad_count +// -- the parser ENDS the expression at the newline and reads `- x` as a fresh statement applying +// unary minus, silently discarding one operand. Measured, not inferred: this exact function +// returned false with the numbers correct, and a reduced case gives `100 \n - 1` == -1 while +// `100 \n + 1` == 101 and `100 \n * 3` == 300. Only `-` is affected, because only `-` has a +// unary form that can legally begin a statement -- the classic automatic-semicolon hazard. +// Receipt and reduced cases: docs/probes/leading_minus_continuation_silently_truncates_2026-08-23.md +fn azifa072_depopulation_is_arithmetically_consistent() -> Bool { + (azifa072_fill_discrepancy.outline_fill_position_count - azifa072_fill_discrepancy.actual_pad_count) + == azifa072_fill_discrepancy.depopulated_position_count + && azifa072_fill_discrepancy.actual_pad_count == azifa072_pad_geometry.pad_count +} + +type SolderTermination { + ball_diameter_before_smt_um: Int + ball_centre_height_before_smt_um: Int +} + +data azifa072_termination: SolderTermination = SolderTermination { + ball_diameter_before_smt_um: 520, + ball_centre_height_before_smt_um: 260, +} + +data azifa072_termination_provenance: GeometryProvenance = CalloutConfirmedByExtraction { + sheet: 2, + wording: "4926 X Ø0.52 SOLDER BALLS BEFORE SMT", + agreement: "the STEP solid models 650 spherical faces at radius exactly 0.26, so the callout diameter and the modelled radius agree without either being read from the other", +} + +// ================= OUTLINE AND KEEPOUT ================= +// +// THE WIDEST PLANE IS ASYMMETRIC AND A KEEPOUT TAKEN FROM THE HOUSING OUTLINE IS WRONG. The body +// is symmetric about the pad-array centre; the plane at +2.38 mm is not, reaching 5.118 mm +// further on +X than on -X. That protrusion is the drawing's 2X FINGER ACCESS -- the actuation +// side -- and it is the single measurement most likely to be missed, because every other outline +// on the part is symmetric and invites the assumption. +type SocketOutline { + housing_bottom_x_um: Int + housing_bottom_y_um: Int + housing_top_x_um: Int + housing_top_y_um: Int + widest_plane_x_um: Int + widest_plane_y_um: Int + widest_plane_height_um: Int + asymmetric_protrusion_plus_x_um: Int + height_above_pcb_before_smt_um: Int +} + +data azifa072_outline: SocketOutline = SocketOutline { + housing_bottom_x_um: 70900, + housing_bottom_y_um: 80900, + housing_top_x_um: 72300, + housing_top_y_um: 82300, + widest_plane_x_um: 77418, + widest_plane_y_um: 82300, + widest_plane_height_um: 2380, + asymmetric_protrusion_plus_x_um: 5118, + height_above_pcb_before_smt_um: 4680, +} + +data azifa072_outline_provenance: GeometryProvenance = ExtractedFromDrawingVectors { + method: "STEP solid AZIFA072_B_220208(LGA4926 SKT)-1, planar point extents at each Z band, expressed relative to the PCB pad plane taken as the solder-ball tangent before SMT", +} + +// ================= WHAT THIS DRAWING DOES NOT ESTABLISH ================= +// +// NAMED HERE RATHER THAN LEFT TO BE REDISCOVERED, and typed rather than written as prose, because +// a footprint release has to be able to ASK whether these are closed. A gap recorded only in a +// README is a gap a generator cannot consult. +type LandPatternGap + = StencilApertureUnread { reason: NonEmptyStr } + | PinOneCornerUnlocated { reason: NonEmptyStr } + | SolderMaskOpeningUnidentified { reason: NonEmptyStr } + +data azifa072_open_gaps: List = [ + StencilApertureUnread { + reason: "sheet 4 carries the STENCIL APERTURE detail at 80:1, but its dimension values are drawn as vector outlines rather than text and the only closed shape recoverable at that scale is the Ø0.46 pad itself. The aperture must be read off the drawing by eye before paste is released.", + }, + PinOneCornerUnlocated { + reason: "sheet 2 carries MARKING FOR Pin1 and the array is demonstrably not symmetric -- the two banks depopulate differently -- so the orientation is recoverable, but no extraction has established WHICH corner is A1 and a guessed A1 rotates the whole board.", + }, + SolderMaskOpeningUnidentified { + reason: "sheet 3's second view draws the same 4926-position lattice with a larger circle measuring about 0.73 to 0.77 mm. No recovered callout attaches a name to it, so whether it is the mask opening, the contact-tip footprint or a keepout is unestablished.", + }, +] + +fn land_pattern_gap_count() -> Int { + count(azifa072_open_gaps) +} + +// A FOOTPRINT MAY NOT EMIT WHILE ANY GAP STANDS -- AND NOTHING TODAY ASKS IT. The rung is stated +// honestly rather than implied by the function's existence: no footprint emitter for this part +// exists in the tree, so the only consumer is the witness that executes this predicate. That +// makes it a real, executing answer to "may it emit" and NOT evidence that anything is prevented. +// Calling it the gate an emitter consults would be the specification-without-execution claim +// DESIGN section 5 names, one step before the inert-lens tier: the machinery exists and nothing +// gates on it. +// +// NEXT-RUNG TRIGGER: the first consumer that turns this land pattern into pads. product.pcb.footprint +// already carries the Pad carrier that would receive them, and it is the module that would have to +// call this before emitting. Until such a caller exists the class sits at mitigatable -- the answer +// is right and unenforced -- and a released footprint is prevented by review, not by construction. +// +// The refusal itself is deliberately not a warning: a paste layer released without its aperture +// and a board rotated by a guessed A1 are both unrecoverable at fabrication, so the failure arm +// refuses rather than proceeding with a default (DESIGN section 5). +fn azifa072_footprint_may_emit() -> Bool { + land_pattern_gap_count() == 0 +} diff --git a/dag/product/altra_motherboard/attachment_stack.dag b/dag/product/altra_motherboard/attachment_stack.dag index 6b7bf606796..1c95c7333f8 100644 --- a/dag/product/altra_motherboard/attachment_stack.dag +++ b/dag/product/altra_motherboard/attachment_stack.dag @@ -242,16 +242,32 @@ fn board_land_pattern_fact_from_obligation(standing: DesignationResolutionStandi } } +// THE ESTABLISHED ARM WAS WRONG AND UNREACHABLE, AND IT BECAME REACHABLE ON 2026-08-23. It +// answered CarriageNotApplicable with the reason "no carriage question is modeled separately once +// a land pattern is established from a cited authority" -- which authority_standing_refusal +// directly contradicts: EstablishedFactHasInapplicableCarriage exists precisely because AN +// ESTABLISHED FACT ALWAYS HAS A CARRIAGE ANSWER. The two functions disagreed in this repository +// for as long as the arm existed, and nothing detected it, because no input could reach the arm +// while the land pattern was unresolved. +// +// This is the reachability-read-as-occupancy class from the other direction. The usual error is +// deleting a live guard because nothing currently lands in it; here an arm nobody could land in +// went unexamined and was simply incorrect, and the first input to arrive found it. That is the +// fail-closed substrate working exactly as intended -- resolving the socket body was the census, +// and what broke is what was load-bearing -- but it is worth naming that the defect predates the +// change that surfaced it rather than being introduced by it. +// +// NormalizedFactsMayBeCarried is the correct answer and not merely a passing one: the type's own +// definition says it means the normalized numerical facts are admitted AND the vendor's +// expression of them is not, which is exactly this layer's state. The extracted pitch, count, +// diameter and 4,926 positions are carried; the vendor's drawing is not. fn carriage_for_board_land_pattern_fact(fact: FactAuthorityStanding) -> RepositoryCarriageStanding { match fact { FactAccessGated { subject: _, access_route: _ } => CarriageNotApplicable { because: "the fact is behind commercial access, so its carriage is governed by the access terms and is not a decision this repository takes separately", } - FactEstablished { authority: _, subject: _ } => - CarriageNotApplicable { - because: "no carriage question is modeled separately once a land pattern is established from a cited authority", - } + FactEstablished { authority: _, subject: _ } => NormalizedFactsMayBeCarried FactUnresolved { what_is_missing: _ } => CarriageNotApplicable { because: "no fact is established for this layer, so there is nothing to decide carriage for", diff --git a/dag/product/altra_motherboard/placement.dag b/dag/product/altra_motherboard/placement.dag index 4b9c8f4f68e..4bde06cd0e2 100644 --- a/dag/product/altra_motherboard/placement.dag +++ b/dag/product/altra_motherboard/placement.dag @@ -36,6 +36,9 @@ import std.spatial_frame { } import product.altra_motherboard.minimal_design { AltraMinimalMotherboard, + DesignIntent, + EngineeringBringUp, + Production, DdrSlotIdentity, ddr_channel_ordinal, ddr_slot_identity_eq, @@ -49,6 +52,7 @@ import product.altra_motherboard.realization { altra_1p_requirement_part_realizations, population_realization_refusals, } +import extdeps.external_authority { ExternalAuthority } import extdeps.land_pattern.types { PackageBodyDimensions } import extdeps.network.ti_dp83867 { dp83867_rgz0048b_body } import extdeps.power.ti_tps53688 { tps53688_rsb0040a_body } @@ -316,16 +320,127 @@ fn realization_placement_refusals(plan: BoardPlacementPlan) -> List RoleRequirement { + match r { + ProcessorSocket => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "the board is an Altra board; without the socket there is no processor attachment at all" }, + } + ProcessorPackage => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "the processor is the subject of the design under every intent" }, + } + MemoryModuleSlot { slot: _ } => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "the slot population is already selected against intent in minimal_design; each slot the topology names is owed under whatever intent produced that topology" }, + } + ProcessorRailSequencer => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "the processor rails have a documented enable order; nothing comes out of reset without something applying it" }, + } + ProcessorPowerStage => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "the part draws its power through a stage that must exist before it runs at all" }, + } + ProcessorPowerGoodSupervisor => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "sequencing without supervision cannot tell a rail that came up from one that did not, which is a silent-wrongness failure in hardware" }, + } + ResetController => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "reset supervision is what makes power-up a defined transition rather than an undefined one" }, + } + BootFirmwareEeprom => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "the processor fetches boot firmware before any board feature exists to be useful" }, + } + FirmwareFlash => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "host firmware storage is on the boot path under every intent" }, + } + BoardControlCpld => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "board control logic carries the sequencing and reset behaviour the discrete parts are wired into" }, + } + DebugConnector => RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "DebugAccess is a named BoardRequirementIdentity in realization.dag, so debug is a requirement this board model already recognises rather than a bring-up convenience. A first draft of this row made it bring-up-only, which would have asserted that a production Altra server is not owed debug access -- a claim no cited document supports and which the requirements model contradicts" }, + } + HostNetworkPhy => RequiredOnlyUnderProduction { + basis: RepositoryDesignPolicy { because: "host networking is what the server is FOR, and is on no path required to bring the processor up; a fixture that must carry a PHY to be admitted is paying for a feature it does not exercise" }, + } + ManagementNetworkPath => RequiredOnlyUnderProduction { + basis: RepositoryDesignPolicy { because: "out-of-band management is a property of a deployed server; a fixture on a bench is managed by the person standing at it" }, + } + StorageEndpoint => RequiredOnlyUnderProduction { + basis: RepositoryDesignPolicy { because: "an NVMe endpoint carries the workload, not the boot path this model requires; a fixture boots from firmware already required above" }, + } + } +} + +// THE ONE PLACE INTENT IS APPLIED, so adding a DesignIntent breaks exactly here and loudly rather +// than in fourteen role arms. +fn requirement_applies_under(req: RoleRequirement, intent: DesignIntent) -> Bool { + match req { + RequiredUnderEveryIntent { basis: _ } => true + RequiredOnlyUnderProduction { basis: _ } => + match intent { + Production => true + EngineeringBringUp => false + } + RequiredOnlyUnderBringUp { basis: _ } => + match intent { + EngineeringBringUp => true + Production => false + } + } +} + +fn role_is_required_under(r: BoardComponentRole, intent: DesignIntent) -> Bool { + requirement_applies_under(req: role_requirement(r: r), intent: intent) +} + +// THE CANDIDATE SET IS ENUMERATED ONCE. Every non-slot role the board can carry, in one list, so +// required_roles filters rather than re-listing -- a second hand-maintained list would be the fork +// that drifts the first time a role is added to one and not the other. +fn every_non_slot_role() -> List { + [ProcessorSocket, ProcessorPackage, BoardControlCpld, BootFirmwareEeprom, FirmwareFlash, + ResetController, ProcessorRailSequencer, ProcessorPowerStage, ProcessorPowerGoodSupervisor, + HostNetworkPhy, ManagementNetworkPath, StorageEndpoint, DebugConnector] +} + fn required_roles(d: AltraMinimalMotherboard) -> List { let slots = fold(topology_slot_identities(t: d.memory.topology), init: [], f: fn(acc, s) { concat(acc, [MemoryModuleSlot { slot: s }]) }) - concat( - [ProcessorSocket, ProcessorPackage, BoardControlCpld, BootFirmwareEeprom, FirmwareFlash, - ResetController, ProcessorRailSequencer, ProcessorPowerStage, ProcessorPowerGoodSupervisor, - HostNetworkPhy, ManagementNetworkPath, StorageEndpoint, DebugConnector], - slots - ) + let gated = fold(every_non_slot_role(), init: [], f: fn(acc, r) { + if role_is_required_under(r: r, intent: d.intent) { concat(acc, [r]) } else { acc } + }) + concat(gated, slots) } fn role_fill_count(plan: BoardPlacementPlan, r: BoardComponentRole) -> Int { diff --git a/dag/test/claim/altra_attachment_stack_witness_test.dag b/dag/test/claim/altra_attachment_stack_witness_test.dag index 4c3846d1fef..43f3d33623e 100644 --- a/dag/test/claim/altra_attachment_stack_witness_test.dag +++ b/dag/test/claim/altra_attachment_stack_witness_test.dag @@ -91,14 +91,27 @@ test fn w_the_board_side_termination_population_follows_the_package() -> Bool { // claim this test was always trying to make. The package sitting in an already-cited datasheet is // exactly what makes the conflation tempting, and asserting it from the established side is a // stronger statement than asserting it from two unknowns. +// INVERTED 2026-08-23 BY THE SOCKET-BODY DRAWING, AND THE CLAIM IT DEFENDS IS UNCHANGED. This +// witness never asserted that the land pattern is unobtainable; it asserted that the PROCESSOR +// PACKAGE does not establish it. Both facts are established now, so the discriminating content +// moved to where it always belonged: they are established by DIFFERENT authorities. A future edit +// that derives the board land pattern from the package's underside -- the exact category error +// this module's header exists to make unwritable -- collapses those two authorities into one and +// fails here. test fn w_a_public_package_does_not_establish_the_board_land_pattern() -> Bool { fact_is_established(f: processor_package_standing.fact) - && !fact_is_established(f: board_land_pattern_standing.fact) + && fact_is_established(f: board_land_pattern_standing.fact) && match board_land_pattern_standing.fact { - FactAccessGated { subject: _, access_route: _ } => true + FactEstablished { authority: land_auth, subject: _ } => + match processor_package_standing.fact { + FactEstablished { authority: pkg_auth, subject: _ } => land_auth != pkg_auth + FactAccessGated { subject: _, access_route: _ } => false + FactUnresolved { what_is_missing: _ } => false + FactStatedOnlyInFigure { figure: _, what_is_drawn: _ } => false + } + FactAccessGated { subject: _, access_route: _ } => false FactUnresolved { what_is_missing: _ } => false FactStatedOnlyInFigure { figure: _, what_is_drawn: _ } => false - FactEstablished { authority: _, subject: _ } => false } } @@ -144,6 +157,11 @@ test fn w_an_unresolved_fact_carries_no_carriage_decision() -> Bool { // asking WHERE to obtain the collateral was told WHAT it is. Both are checked, and the // route is checked as an authority rather than as text — which is what makes the swap // unwritable now rather than merely absent. +// +// The land-pattern blocker went from "commercial" to "none" on 2026-08-23 when the socket vendor +// supplied the drawing. The witness still discriminates all three blocker KINDS -- that is what it +// is named for -- and the reference-board collateral below still carries the commercial one, so +// no arm of blocker_kind lost its coverage when this layer stopped being blocked. test fn w_the_three_blocker_kinds_are_distinct() -> Bool { let package_blocker = match layer_blocker(row: processor_package_standing) { Absent => "none" @@ -154,7 +172,7 @@ test fn w_the_three_blocker_kinds_are_distinct() -> Bool { Present { value: b } => blocker_kind(b: b) } package_blocker == "none" - && land_blocker == "commercial" + && land_blocker == "none" && undecided_carriage_blocker() == "redistribution" && match reference_board_collateral_standing() { FactAccessGated { subject: sub, access_route: route } => @@ -183,10 +201,19 @@ fn undecided_carriage_blocker() -> String { } } -// THE NDA BOUNDARY IS THE REFERENCE BOARDS, NOT THE PACKAGE. Stated as an executed comparison -// rather than as prose, because the prose version of this claim was already believed once while -// being false. -test fn w_exactly_one_attachment_layer_is_behind_the_nda_boundary() -> Bool { +// NO ATTACHMENT LAYER IS BEHIND THE NDA BOUNDARY ANY MORE, AND THAT IS THE POINT OF THE RENAME. +// This asserted "exactly one" while the board land pattern's only route ran through Ampere +// Customer Connect. The socket vendor answered on 2026-08-23, so the count is now zero and the +// witness is renamed rather than edited in place: a witness whose name says ONE while it asserts +// ZERO is a stale claim that greps as a live one, which is the positional-citation failure applied +// to test names. +// +// The claim it defends survives intact and is still executed rather than asserted in prose: the +// land pattern is reached through a route this repository can publish, so the layer that was +// gated is now established. If any layer regresses to FactAccessGated -- a future part whose only +// geometry sits behind Customer Connect -- the count goes non-zero and this fails, which is +// exactly the alarm the original witness existed to raise. +test fn w_no_attachment_layer_is_behind_the_nda_boundary() -> Bool { let nda_layers = fold(attachment_stack, init: 0, f: fn(acc, row) { match row.fact { FactAccessGated { subject: _, access_route: _ } => acc + 1 @@ -195,10 +222,10 @@ test fn w_exactly_one_attachment_layer_is_behind_the_nda_boundary() -> Bool { FactStatedOnlyInFigure { figure: _, what_is_drawn: _ } => acc } }) - nda_layers == 1 + nda_layers == 0 && match board_land_pattern_standing.fact { - FactAccessGated { subject: _, access_route: _ } => true - FactEstablished { authority: _, subject: _ } => false + FactEstablished { authority: _, subject: _ } => true + FactAccessGated { subject: _, access_route: _ } => false FactUnresolved { what_is_missing: _ } => false FactStatedOnlyInFigure { figure: _, what_is_drawn: _ } => false } @@ -223,7 +250,7 @@ test fn w_every_attachment_layer_is_open_and_says_why() -> Bool { } } }) - layers == 6 && count_of(xs: open_blockers()) == 5 && package_resolved && others_blocked + layers == 6 && count_of(xs: open_blockers()) == 4 && package_resolved && others_blocked } // The layers are distinguishable rather than six spellings of one thing. diff --git a/dag/test/claim/altra_pcb_world_svg_witness_test.dag b/dag/test/claim/altra_pcb_world_svg_witness_test.dag index c6ab2f62b49..a6e7de84f3f 100644 --- a/dag/test/claim/altra_pcb_world_svg_witness_test.dag +++ b/dag/test/claim/altra_pcb_world_svg_witness_test.dag @@ -491,6 +491,12 @@ test fn w_every_world_component_identity_appears_in_the_scene() -> Bool { } } +// THE BOARD LAND PATTERN DROPPED OUT OF THIS LIST ON 2026-08-23 AND THAT IS THE CORRECT OUTCOME. +// The label is emitted per OPEN obligation, so a resolved layer has no label to find; asserting +// its presence would now be asserting that a solved problem is still unsolved. The two layers that +// remain open keep their assertions, and the count conjunct is what stops this from silently +// becoming weaker: it ties the number of emitted labels to the obligation population rather than +// to a list someone remembered to update, so a layer resolving or regressing moves both together. test fn w_mounting_and_socket_attachment_obligations_appear() -> Bool { match world_or_empty() { Absent => false @@ -498,30 +504,32 @@ test fn w_mounting_and_socket_attachment_obligations_appear() -> Bool { match scene_or_empty() { Absent => false Present { value: s } => - string_contains(s: s, pattern: "attachment: mounting") && string_contains(s: s, pattern: "attachment: socket") && string_contains(s: s, pattern: "attachment: board land pattern") && count_substring(haystack: s, needle: "class=\"pcb-label-attachment-obligation\"") == pcb_attachment_obligation_count(p: pcb_world_physical(w: w)) + string_contains(s: s, pattern: "attachment: mounting") && string_contains(s: s, pattern: "attachment: socket") && !string_contains(s: s, pattern: "attachment: board land pattern") && count_substring(haystack: s, needle: "class=\"pcb-label-attachment-obligation\"") == pcb_attachment_obligation_count(p: pcb_world_physical(w: w)) } } } -// THE BOARD LAND PATTERN IS BEHIND A COMMERCIAL GATE. The standing is projected from -// extdeps.cpu_attachment.ilm4926 ilm4926_resolution_obligations.board_land_pattern, which names -// Altra PCB Layout Guidelines on Customer Connect as the authority (platform spec §4.2.2/4.3.2). -test fn w_the_board_land_pattern_is_behind_a_commercial_gate() -> Bool { +// THE BOARD LAND PATTERN IS NO LONGER AN OPEN OBLIGATION, AND THE WITNESS INVERTED RATHER THAN +// WEAKENED. It asserted the layer sat behind a commercial gate, because its only route ran through +// Ampere Customer Connect. The socket vendor supplied the geometry on 2026-08-23, so the layer is +// established, its carriage is decided, subject_blocker returns Absent for it, and it drops out of +// the obligation list entirely. +// +// ASSERTING ITS ABSENCE ALONE WOULD BE A WEAKER TEST THAN THE ONE IT REPLACES, so the second half +// is what keeps it honest: obligations still EXIST for other layers, and the fold that produced +// this one still discriminates causes. Without that conjunct this witness would also pass if +// attachment_obligations were empty for a reason having nothing to do with the land pattern -- +// an empty-observation narrow, which is the failure mode DESIGN names as strictly worse than the +// widen it forbids, because a widen is merely expensive and a narrow is silently uncovered. +test fn w_the_board_land_pattern_is_no_longer_an_open_obligation() -> Bool { match world_or_empty() { Absent => false Present { value: w } => - fold(pcb_world_physical(w: w).attachment_obligations, init: false, f: fn(acc, a) { - acc || match a.cause { - CommercialAccess { subject: sub } => - (a.layer as String) == "board land pattern" && (sub as String) != "" - DrawingMustBeRead { figure: _, what_is_drawn: _ } => false - MissingDocument { what_is_missing: _ } => false - LegalCarriage { reason: _ } => false - UnselectedPart { because: _ } => false - StandingIsSelfContradictory { what_is_wrong: _ } => false - NamedAttachmentTypePartUnresolved { designation: _, missing: _ } => false - } + let obligations = pcb_world_physical(w: w).attachment_obligations + let land_still_open = fold(obligations, init: false, f: fn(acc, a) { + acc || (a.layer as String) == "board land pattern" }) + !land_still_open && list_length(items: obligations) > 0 } } diff --git a/dag/test/claim/altra_placement_witness_test.dag b/dag/test/claim/altra_placement_witness_test.dag index 5151e4ed371..6ba3c8b5f35 100644 --- a/dag/test/claim/altra_placement_witness_test.dag +++ b/dag/test/claim/altra_placement_witness_test.dag @@ -1,6 +1,6 @@ module test.claim.altra_placement_witness -import std.types { Bool, String, NonEmptyStr, List } +import std.types { Bool, String, NonEmptyStr, List, list_length } import std.integer { Int } import std.decl_ref { DeclarationRef, declaration_ref_eq, decl_ref } import std.measure { micrometer_count } @@ -8,6 +8,19 @@ import std.affine_space { point2 } import std.orthogonal_geometry { OrthogonalReady, OrthogonalRefused } import product.altra_motherboard.placement { BoardControlCpld, + RoleRequirement, + RoleRequirementBasis, + RequiredUnderEveryIntent, + RequiredOnlyUnderProduction, + RequiredOnlyUnderBringUp, + RepositoryDesignPolicy, + role_requirement, + requirement_applies_under, + role_is_required_under, + every_non_slot_role, + HostNetworkPhy, + ManagementNetworkPath, + StorageEndpoint, FrameRegistryEstablished, FrameRegistryRefused, altra_frame_registry, @@ -71,6 +84,7 @@ import product.altra_motherboard.minimal_design { DimmSlotPosition, FirstDimmOnChannel, MemoryConfiguration, + EngineeringBringUp, Production, SecondDimmOnChannel, altra_1p_minimum, @@ -636,3 +650,90 @@ test fn w_the_board_frame_registry_is_established_not_silently_empty() -> Bool { FrameRegistryRefused { cause: _ } => false } } + + +// ================= INTENT GATES THE ROLE SET, NOT ONLY THE CHANNEL COUNT ================= + +// THE THREE PRODUCTION FEATURES DROP OUT OF A BRING-UP BOARD, and nothing else does. This is the +// claim the change exists to make: a fixture is not obliged to carry a host PHY, an out-of-band +// management path or an NVMe endpoint, none of which is on any path required to bring the +// processor out of reset. The count is asserted BOTH ways rather than only for bring-up, because +// a gate that dropped roles under every intent would satisfy a one-sided check while quietly +// removing them from the production board too. +test fn w_bring_up_drops_exactly_the_three_production_features() -> Bool { + let prod = altra_1p_minimum + let fixture = AltraMinimalMotherboard { + intent: EngineeringBringUp, + memory: prod.memory, + pcie_lanes_broken_out: prod.pcie_lanes_broken_out, + } + let prod_roles = list_length(items: required_roles(d: prod)) + let fixture_roles = list_length(items: required_roles(d: fixture)) + prod_roles - fixture_roles == 3 + && role_is_required_under(r: HostNetworkPhy, intent: Production) + && !role_is_required_under(r: HostNetworkPhy, intent: EngineeringBringUp) + && role_is_required_under(r: ManagementNetworkPath, intent: Production) + && !role_is_required_under(r: ManagementNetworkPath, intent: EngineeringBringUp) + && role_is_required_under(r: StorageEndpoint, intent: Production) + && !role_is_required_under(r: StorageEndpoint, intent: EngineeringBringUp) +} + +// THE BOOT PATH IS NOT NEGOTIABLE BY INTENT. Power sequencing, supervision, reset, firmware and +// the socket itself are required under BOTH intents, and this asserts it over the whole role +// coproduct rather than over a list someone remembered to write: every role that is not one of the +// three features above must survive the bring-up gate. A future edit that makes the power-good +// supervisor bring-up-only -- the kind of "minimisation" that produces a board which cannot tell a +// rail that came up from one that did not -- fails here without anyone having to name that role. +test fn w_every_role_but_the_three_features_survives_the_bring_up_gate() -> Bool { + fold(every_non_slot_role(), init: true, f: fn(acc, r) { + let is_feature = roles_equal(a: r, b: HostNetworkPhy) + || roles_equal(a: r, b: ManagementNetworkPath) + || roles_equal(a: r, b: StorageEndpoint) + if is_feature { + acc && !role_is_required_under(r: r, intent: EngineeringBringUp) + } else { + acc && role_is_required_under(r: r, intent: EngineeringBringUp) + && role_is_required_under(r: r, intent: Production) + } + }) +} + +// REACHABILITY CONTROL FOR THE ARM NO ROLE CURRENTLY OCCUPIES. RequiredOnlyUnderBringUp is carried +// by the type and by requirement_applies_under, and after the DebugConnector row was corrected to +// RequiredUnderEveryIntent no role uses it. That makes it a QUIET arm, not a dead one, and the +// distinction is decidable rather than a matter of opinion: the state is authorable here, so the +// arm can be driven and its behaviour observed. An arm whose red could not be produced anywhere a +// check can run would be a decoration -- permanently green by construction and worse than absent, +// because it would be cited as coverage. +test fn w_red_the_bring_up_only_arm_is_reachable_and_discriminates() -> Bool { + let planted = RequiredOnlyUnderBringUp { + basis: RepositoryDesignPolicy { because: "planted: no production role currently claims this arm" }, + } + let every = RequiredUnderEveryIntent { + basis: RepositoryDesignPolicy { because: "planted control" }, + } + let prod_only = RequiredOnlyUnderProduction { + basis: RepositoryDesignPolicy { because: "planted control" }, + } + requirement_applies_under(req: planted, intent: EngineeringBringUp) + && !requirement_applies_under(req: planted, intent: Production) + && requirement_applies_under(req: every, intent: EngineeringBringUp) + && requirement_applies_under(req: every, intent: Production) + && !requirement_applies_under(req: prod_only, intent: EngineeringBringUp) + && requirement_applies_under(req: prod_only, intent: Production) +} + +// MEMORY SLOTS FOLLOW THE TOPOLOGY, NOT THE GATE. The slot roles are already selected against +// intent one layer up, where minimal_design refuses a debug-only channel count under production +// intent. This asserts the two mechanisms compose rather than double-count: changing intent alone, +// with the topology held fixed, must not add or remove a single memory slot. +test fn w_the_role_gate_does_not_touch_the_memory_slots() -> Bool { + let prod = altra_1p_minimum + let fixture = AltraMinimalMotherboard { + intent: EngineeringBringUp, + memory: prod.memory, + pcie_lanes_broken_out: prod.pcie_lanes_broken_out, + } + memory_role_count(d: prod) == memory_role_count(d: fixture) + && memory_role_count(d: prod) == 4 +} diff --git a/dag/test/claim/ilm4926_designation_witness_test.dag b/dag/test/claim/ilm4926_designation_witness_test.dag index d421ba912e0..f3275128f81 100644 --- a/dag/test/claim/ilm4926_designation_witness_test.dag +++ b/dag/test/claim/ilm4926_designation_witness_test.dag @@ -53,6 +53,12 @@ import extdeps.cpu_attachment.ilm4926 { SocketBodyStanding, standing_is_established, ocp_mt_jade_specification_authority, + azifa072_drawing_authority, + lga4926_footprint_may_release, +} +import extdeps.cpu_attachment.lotes_azifa072 { + azifa072_footprint_may_emit, + land_pattern_gap_count, } import v2.std.live_tree { LiveTreeDisposition, SubstrateInputsOnly } @@ -111,32 +117,42 @@ test fn w_red_one_publisher_twice_is_not_independent_attestation() -> Bool { // THE FOUR BOARD-DESIGN AXES ARE UNRESOLVED SUMS, NOT NONEMPTY STRINGS — read by // match on each field rather than a Bool predicate over the coproduct. -// THE SOCKET BODY IS UNIDENTIFIED ON BOTH OF ITS AXES, and the land pattern with it. These are -// read through the socket-body constituent rather than off a flat record, which is the point of -// the restructure: there is no top-level vendor_identity to answer for the whole assembly. -test fn w_the_socket_body_is_unidentified_on_every_axis() -> Bool { +// THE SOCKET BODY IS NOW IDENTIFIED ON EVERY AXIS, AND THE DESIGNATOR IS STILL NOT EXPANDED. +// This witness inverted on 2026-08-23 when Lotes supplied AZIFA072-P001CCS. It is kept rather +// than deleted because the pairing is the whole content: three axes flipped and the fourth did +// not, and a reader who assumes a part number closes the referent question needs to see exactly +// that combination assert. A part number resolves what to order; it does not tell you what the +// letters I-L-M stand for, and no cited document still does. +test fn w_the_socket_body_is_identified_while_the_designator_stays_unexpanded() -> Bool { let a = ilm4926_attachment_standing - !standing_is_established(s: a.socket_body.vendor_identity) - && !standing_is_established(s: a.socket_body.orderable_part_number) - && !standing_is_established(s: attachment_board_land_pattern(a: a)) - && !attachment_socket_body_is_identified(a: a) + standing_is_established(s: a.socket_body.vendor_identity) + && standing_is_established(s: a.socket_body.orderable_part_number) + && standing_is_established(s: attachment_board_land_pattern(a: a)) + && attachment_socket_body_is_identified(a: a) && !designation_referent_is_resolved(referent: ilm4926_referent) } -// THE RETENTION ASSEMBLY RESOLVES; THE SOCKET BODY DOES NOT. Lotes is a publisher of record for -// its own catalogue, so AZIF0222 establishes both retention axes. This witness is the pair to -// that: establishing them must leave every socket-body axis exactly where it was, because the -// socket body is a different item and it is the one that carries the pads. -test fn w_the_retention_assembly_resolves_without_touching_the_land_pattern() -> Bool { +// TWO CONSTITUENTS, TWO AUTHORITIES, AND THE WITNESS IS THAT THEY STAYED SEPARATE. The retention +// assembly is cited to the Lotes catalogue page; the socket body is cited to the Lotes customer +// drawing. Both are Lotes, and that is exactly why this asserts the authorities are DIFFERENT +// declarations: one vendor supplying two parts is still two subjects, and the failure this +// guards is a later edit collapsing them onto one citation because the vendor name matches. +test fn w_the_two_constituents_resolve_to_their_own_separate_authorities() -> Bool { let a = ilm4926_attachment_standing (match a.retention_assembly.orderable_part_number { DesignationFactEstablished { value: _, authority: auth } => auth == lotes_azif0222_product_authority DesignationFactUnresolved { reason: _, next_authority_to_consult: _ } => false }) + && (match a.socket_body.orderable_part_number { + DesignationFactEstablished { value: _, authority: auth } => auth == azifa072_drawing_authority + DesignationFactUnresolved { reason: _, next_authority_to_consult: _ } => false + }) + && (match attachment_board_land_pattern(a: a) { + DesignationFactEstablished { value: _, authority: auth } => auth == azifa072_drawing_authority + DesignationFactUnresolved { reason: _, next_authority_to_consult: _ } => false + }) && standing_is_established(s: a.retention_assembly.vendor_identity) - && !standing_is_established(s: attachment_board_land_pattern(a: a)) - && !standing_is_established(s: a.socket_body.vendor_identity) - && !standing_is_established(s: a.socket_body.orderable_part_number) + && lotes_azif0222_product_authority != azifa072_drawing_authority } // MOUNTING HARDWARE IS ITS OWN CONSTITUENT AND IS NOT COVERED BY THE RETENTION PART. Whether the @@ -145,14 +161,26 @@ test fn w_the_retention_assembly_resolves_without_touching_the_land_pattern() -> test fn w_mounting_hardware_is_separately_unresolved() -> Bool { let a = ilm4926_attachment_standing !standing_is_established(s: a.mounting_hardware.orderable_part_number) - && attachment_unresolved_constituent_count(a: a) == 2 + && attachment_unresolved_constituent_count(a: a) == 1 } -// NO FOOTPRINT MAY EMIT. The gate is conjunctive on socket-body identity AND land pattern, so -// resolving the retention assembly cannot open it -- which is the failure this whole module exists -// to prevent: a released pad array for a part nobody has named. -test fn w_no_footprint_may_emit_while_the_socket_body_is_unnamed() -> Bool { - !attachment_footprint_may_emit(a: ilm4926_attachment_standing) +// ESTABLISHED IS NOT COMPLETE, AND THIS WITNESS IS THE PAIR THAT SAYS SO. The standing-level +// gate now OPENS -- the socket body is identified and its land pattern established, so a +// predicate over the standing has nothing left to refuse. The release gate still REFUSES, +// because three geometry gaps stand in the socket-body module. Both halves are asserted +// together because either alone is misleading: the first read alone says ship it, the second +// read alone hides that the citations actually landed. +// +// This is the specimen for the failure caught on the run that introduced it: the standing gate +// flipped to true the moment the last citation arrived, while the stencil aperture was unread +// and the Pin 1 corner unlocated. Establishment is a property of a fact's grounding; +// releasability is a property of a deliverable's completeness. A gate reading only the first +// permits as soon as the paperwork is done. +test fn w_the_standing_gate_opens_while_the_release_gate_still_refuses() -> Bool { + attachment_footprint_may_emit(a: ilm4926_attachment_standing) + && !lga4926_footprint_may_release() + && !azifa072_footprint_may_emit() + && land_pattern_gap_count() == 3 } // RED control: the emit gate is reachable. A predicate that can only answer false would prove @@ -281,16 +309,24 @@ test fn w_red_an_official_attestation_would_register_as_one() -> Bool { && part_referent_is_assigned(c: official) } -// THE DRAWING IS MOUNTING GEOMETRY, NOT A LAND PATTERN, and this witness is what stops the -// attachment-stack progress from being read as land-pattern progress. The retention drawing -// carries no pad array, so the board land pattern obligation must remain unresolved even though -// a real dimensioned drawing for this designation now exists. +// THE RETENTION DRAWING IS MOUNTING GEOMETRY, NOT A LAND PATTERN, and this witness is what stops +// attachment-stack progress from being read as land-pattern progress. Its second conjunct changed +// on 2026-08-23 and the reason is worth stating: the land pattern IS now established, so asserting +// it is unresolved would be asserting a stale fact. What the witness actually defends is that the +// retention drawing did not establish it -- so it now asserts the land pattern's authority is the +// SOCKET-BODY drawing and specifically NOT the retention catalogue page. That keeps the original +// claim exactly (mounting geometry establishes no pad array) and states it against the world that +// exists rather than the one that did. test fn w_retention_drawing_does_not_establish_the_land_pattern() -> Bool { (match lga4926_retention_drawing_scope { MountingAndOutlineGeometry => true BoardSidePadArray => false }) - && !standing_is_established(s: attachment_board_land_pattern(a: ilm4926_attachment_standing)) + && (match attachment_board_land_pattern(a: ilm4926_attachment_standing) { + DesignationFactEstablished { value: _, authority: auth } => + auth == azifa072_drawing_authority && auth != lotes_azif0222_product_authority + DesignationFactUnresolved { reason: _, next_authority_to_consult: _ } => false + }) } // THE TWO ROUTES ARE DISTINGUISHED BY CARRIAGE, NOT BY PREFERENCE. Obtaining the gated Ampere diff --git a/docs/extdeps/lotes_azifa072/README.md b/docs/extdeps/lotes_azifa072/README.md new file mode 100644 index 00000000000..e48df37f702 --- /dev/null +++ b/docs/extdeps/lotes_azifa072/README.md @@ -0,0 +1,140 @@ +# Lotes AZIFA072-P001CCS — LGA4926 socket body + +The socket-body part for the LGA4926 designation, and the customer drawing that carries its +board land pattern. This closes the constituent that `extdeps.cpu_attachment.ilm4926` had left +unresolved since the module was written: Lotes AZIF0222 is the ILM + backplate assembly, and +this is the *different* orderable item that receives the processor and solders to the board. + +## Provenance + +Supplied by Lotes in direct response to the request recorded in +`lga4926_land_pattern_public_route` ("the socket-body part number that mates with AZIF0222, then +its customer drawing or recommended PCB layout"). Not access-gated; no confidentiality marking +appears in the document. This is the public-route resolution, not the NDA route — the geometry +below is carriable. + +| | | +|---|---| +| Part number | `AZIFA072-P001CCS` | +| Drawing number | `GAP-AZIFA072` | +| Title | LGA4926 SOCKET | +| Revision | 2 (ECN N230045, 04/10'2023) | +| Prior revisions | 1 → CNDR2100660 (04/15'2022), N220063 (07/20'2022) | +| Sheets | 5, A4, units mm | +| Drawn / checked / approved | WU YONGQUAN / ZHIHUA HUI / GRANDO ZHANG | +| 3D | `AZIFA072_B_20220208 (LGA4926 Socket).STEP`, AP214, SolidWorks 2019, mm | + +## Files + +- `lga4926_pcb_pads.csv` — 4,926 PCB pad centres in mm, extracted from sheet 3 (below) +- `lga4926_pad_array.svg` — the same array rendered, for eyeball verification + +**Neither the drawing nor the STEP solid is committed, and the drawing's absence is a policy +decision rather than a size one.** `product.altra_motherboard.attachment_stack` states it on +`RepositoryCarriageStanding`, whose deliberately absent fourth arm is `SourceExpressionMayBeCarried`: +copying a vendor's PDF, figure, prose or table layout is refused for **every** subject, not chosen +per subject. The operator's clearance covered confidentiality — there is no NDA on this part — +which is a different question from whether this repository carries a vendor's expression of its +own facts. An earlier revision of this directory committed the PDF; both conditions had to hold +and only the first had been checked. + +What is carried here is what `NormalizedFactsMayBeCarried` admits: the normalized numerical facts, +extracted and cross-checked. To obtain the source documents, ask Lotes for **GAP-AZIFA072 +revision 2** (the STEP is `AZIFA072_B_20220208 (LGA4926 Socket)` = socket body +`AZIFA072_B_220208(LGA4926 SKT)-1` + protective cap `SKT4926 CAP_A_20220107`). + +## The land pattern + +Extracted from the sheet-3 pad view, whose vector content draws every pad individually. + +| Property | Value | Source | +|---|---|---| +| Pad count | **4,926** | drawing callout `4926 X` **and** the extracted element count, independently | +| Pad diameter | **Ø0.46 ±0.05 mm** | sheet-3 callout `4926 X Ø0.46 ±0.05 PCB PADS`; confirmed by the sheet-4 detail circle measuring 0.4599 mm at its stated 80:1 | +| Lattice | **hexagonal / staggered**, alternate rows offset 0.5 mm in X | extracted | +| Column pitch | **1.000 mm** (within a row) | extracted; fitted 0.99704 of nominal | +| Row pitch | **0.870 mm** | extracted; = 1.000 × cos 30° = 0.8660 nominal | +| Nearest-neighbour spacing | **1.00 mm** | derived: √(0.5² + 0.87²) | +| Array extent | **63.449 × 75.470 mm** | extracted | +| Rows | 84, in two banks of 42 | extracted | +| Columns | 64 max per row | extracted | +| Bank gap | 4.13 mm, no row between, banks in different X phase | extracted | +| Central void | ≈13.9 mm wide × ≈25 mm tall, centred | extracted | + +`lga4926_pcb_pads.csv` carries all 4,926 centres, origin at the array centre, +X right / +Y up +in the STEP part frame (verified — see cross-check). + +### Solder ball / termination + +| Property | Value | Source | +|---|---|---| +| Solder ball diameter, before SMT | **Ø0.52 mm** | sheet-2 callout `4926 X Ø0.52 SOLDER BALLS BEFORE SMT`; the STEP models 650 spherical faces at exactly r = 0.26 | +| Ball centre height above PCB | 0.26 mm (before SMT) | STEP | + +## Cross-check — two independent sources agree + +The drawing's vector pad array and the STEP solid's solder-ball centres were extracted by +separate paths and compared. They are the same array: + +- array extent from the PDF: 63.449 × 75.470 mm; from the STEP: 63.44 × 75.47 mm +- of the 650 ball positions the STEP models, **642 land within 0.25 mm** of an extracted pad +- median deviation **0.019 mm**, p95 0.051 mm, max 0.49 mm + +This is a real cross-validation, not a restatement: nothing in the PDF extraction consulted the +STEP, or the reverse. The eight outliers sit at the array's chamfered corners, where the +per-row index fit accumulates the most rounding. + +## Socket outline and stack-up + +All Z given relative to the PCB pad plane (= the solder-ball tangent before SMT), from the STEP. + +| Feature | Value | +|---|---| +| Housing bottom flange | 70.900 × 80.900 mm, at +0.18 mm | +| Housing top | 72.300 × 82.300 mm, at +4.68 mm | +| Widest plane | 77.418 × 82.300 mm, at +2.38 mm | +| Overall height above PCB, before SMT | **4.68 mm** | + +The housing is symmetric about the pad-array centre in both X and Y. The widest plane is **not** +symmetric: it reaches 41.268 mm on +X against 36.150 mm on −X, a 5.118 mm protrusion on one side +only. That is the actuation side, and it is the drawing's `2X FINGER ACCESS`. A board keepout +taken from the symmetric outline will be 5.1 mm short on that edge. + +## What is on each sheet + +1. Socket housing, section A-A, `4926 X CONTACT TIPS`, `4926 X CONTACT POINTS AFTER SMT`, + `2X FINGER ACCESS`, `STANDOFF GAP`, `4926 X SOLDER BALL POSITION`, before/after SMT states +2. `4926 X Ø0.52 SOLDER BALLS BEFORE SMT`, section B-B, `MARKING FOR Pin1`, contact tip free + height, date code, `PICK AND PLACE TOOLING KEEP-IN ZONE`, housing/cap 1.1 / 1.2, 3D view 1:20 +3. `SOCKET HOUSING OUTLINE`, `PACKAGE OUTLINE`, `4926 X Ø0.46 ±0.05 PCB PADS` — **the land pattern** +4. `STENCIL APERTURE` and `PCB PAD` details at 80:1 — **the paste layer** +5. Packaging: 4 sockets per tray, 40 per inner box, 160 per outer box + +## Known gaps — read these before releasing a footprint + +1. **Stencil aperture dimension not extracted.** Sheet 4 carries it, but its dimension values are + drawn as vector outlines rather than text, and the only closed shape recoverable at 80:1 is the + Ø0.46 pad itself. Read the aperture off the PDF by eye before releasing paste. +2. **Pin A1 not located.** Sheet 2 carries `MARKING FOR Pin1`; its position was not extracted. + The array is not symmetric — the two banks have visibly different depopulation patterns — so + orientation is recoverable from the pad map, but the A1 corner has not been *established* + against the drawing and must not be guessed. +3. **Solder-mask openings unconfirmed.** Sheet 3's second view draws the same 4,926-position + lattice with a larger circle measuring ≈0.73–0.77 mm. That is most likely the mask opening or + the contact-tip footprint, but no callout was recovered attaching a name to it, so it is + recorded as unidentified rather than assumed. +4. **A few rows near the bank boundary.** Row clustering merged a handful of rows whose drawn + Y positions sit closer than the 0.87 mm pitch. The total is exactly 4,926 and no position is + duplicated or dropped, so this affects which row a pad is *labelled* with, not where it is. +5. **The interior is not derivable from the STEP alone.** The solid models only the perimeter of + the ball field — 650 of 4,926. A naive lattice fill of its outline gives 5,285, over by 359. + The interior voids come from the drawing and only from the drawing. + +## Method + +Both extractions are reproducible from the drawing named above, which is not committed here (see +**Files**). The PDF's page content was decompressed, +its object streams expanded, per-font `ToUnicode` CMaps applied for text, and path operators +replayed under a tracked CTM for geometry; pads are the 9-vertex closed subpaths of the sheet-3 +upper view, and scale was fixed by fitting the within-row column pitch to 1.000 mm and confirmed +independently against the 80:1 detail circle. diff --git a/docs/extdeps/lotes_azifa072/lga4926_pad_array.svg b/docs/extdeps/lotes_azifa072/lga4926_pad_array.svg new file mode 100644 index 00000000000..67ec755e80b --- /dev/null +++ b/docs/extdeps/lotes_azifa072/lga4926_pad_array.svg @@ -0,0 +1,4929 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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00000000000..ef218ececc6 --- /dev/null +++ b/docs/probes/leading_minus_continuation_silently_truncates_2026-08-23.md @@ -0,0 +1,91 @@ +# A continuation line beginning with `-` silently truncates the expression + +**Found:** 2026-08-23, while adding an arithmetic consistency check to +`extdeps.cpu_attachment.lotes_azifa072` (gunbc#9061). +**Class:** silent wrongness — below the guarantee ladder's floor, not a rung on it (DESIGN §4b/§5). +**Live corpus exposure:** zero. The only instance was the one that found it, now fixed. + +## The defect + +An expression continued onto a following line whose first token is `-` is not continued. The +parser ends the expression at the newline and reads the continuation as a **fresh statement** +applying unary minus. One operand is discarded. No diagnostic is produced at any severity. + +``` +fn minus_leading() -> Int { + 100 + - 1 +} +``` + +`minus_leading()` returns **-1**. The `100` is evaluated and dropped; the value of the function is +the last statement, `-1`. + +In a `let` binding the discarded half is the other one: + +``` +let multi = d.outline_fill_position_count + - d.actual_pad_count +``` + +`multi` binds to `d.outline_fill_position_count` alone — measured at 5285 where 359 was intended — +because the `- d.actual_pad_count` line becomes a separate discarded statement. + +## Only `-`, and the reason is the point + +| reduced case | returns | correct | +|---|---|---| +| `100` ⏎ `- 1` | **-1** | ✗ (expected 99) | +| `100` ⏎ `+ 1` | 101 | ✓ | +| `100` ⏎ `* 3` | 300 | ✓ | +| `100 -` ⏎ `1` | 99 | ✓ | + +`+` and `*` continue correctly, and a **trailing** `-` continues correctly. Only a **leading** `-` +fails, because only `-` has a unary form that can legally begin a statement. This is the classic +automatic-semicolon-insertion hazard: the parser continues an expression across a newline exactly +when the next token *cannot* start a statement, and `- x` can. + +## Why this is below the floor rather than a low rung + +The failure is not a refusal, a wrong diagnostic, or a degraded answer. It is a **fabricated +plausible output**: a total, type-correct function that returns a confidently wrong value. It +type-checks, it compiles with zero diagnostics at any severity, and it reads correctly to a +reviewer — the wrong parse is invisible in the source that produced it. DESIGN §5 places silent +wrongness outside the ladder entirely. + +It was caught only because the check was **executed** and its answer disagreed with hand +arithmetic. A `.contains()` grep, a typecheck, or a review pass would each have let it through, +which is the specification-without-execution trap in its purest live form. + +## Blast radius, measured + +A grep for continuation lines beginning with `-` across `dag/` and `src/v2/` returns 13 hits. Twelve +are prose bullets inside string literals — markdown lists in `std/realization_schedule.dag`, +`gunbc/tools/review_codex.dag`, `gunbc/ci_release_bins.dag` — where the text is data and the parse +is irrelevant. The thirteenth was the instance in this PR. So the mechanism is confirmed and the +current corpus exposure is zero. + +Zero exposure is not zero risk. The corpus writes multi-line boolean chains with leading `&&` +constantly, so the *style* the hazard punishes is house style; it is only the operator that is rare. +The first arithmetic expression someone splits that way will be silently wrong. + +## What was NOT done, and why + +The parser is not fixed here. This is `src/v1`, whose admission test is service to the v2 self-host +program (DESIGN §3, v1 maintenance standing) — a lexer or statement-boundary change is neither that +nor in the scope of the pull request that found it, and it needs its own review against v2's grammar +rather than a drive-by in a socket-geometry change. + +The instance was repaired by parenthesising the subtraction on one line, with the reason recorded at +the call site rather than left as unexplained formatting. That is a repair of the instance, not of +the class, and naming the difference is the point of this probe: **the class is open.** + +## Next-rung trigger + +A statement-boundary rule that refuses an ambiguous continuation rather than silently choosing one +of its two readings. The fail-closed form is available and cheap: where a newline is followed by a +token that could either continue the expression or begin a statement, refuse with a located +diagnostic naming both readings and requiring parentheses or an explicit terminator. That converts +this from silent wrongness to a typed refusal — from below the floor to *structurally guaranteed* — +and, unlike a precedence tweak, cannot change the meaning of any program that currently parses the +way its author intended.