From ceca212e435286373e41c25e796a9613d47cc6a7 Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 21:20:42 +0000 Subject: [PATCH 01/14] WIP: gpu accelerated .dag --- docs/plans/accelerator-demo-roundtrip.md | 85 ++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 docs/plans/accelerator-demo-roundtrip.md diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md new file mode 100644 index 00000000000..5ec110a1f26 --- /dev/null +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -0,0 +1,85 @@ +# Accelerator-kernel demo round-trip — show the daglang moat in XLA's terms + +**Status:** design draft (operator-directed tangent, 2026-06-29). Expansion-band showcase, not a stability-band gate. +**Displaced cost (the §6 deliverable):** a communicable, *runnable* artifact that proves the daglang architecture's power to an accelerator/array-compiler audience (NVIDIA / the XLA team) **in their own vocabulary** — fusion, layout assignment, buffer assignment, numerical-semantics preservation — without making them learn the substrate first. The pain it removes: "the architecture is powerful but I can't show it to a hardware/compiler audience in 60 seconds." This is a *small, honest subset* chosen because it is the easiest slice to communicate, not because it is the deepest. + +This draft is downstream of [DESIGN.md](../../DESIGN.md) §4 (one grammar, both directions), §5 (fail-closed honesty boundary), §7 (medium-agnostic), and the [model↔realization fork](model-realization-fork.md) / [realization-measurement loop](realization-measurement-loop.md). It is **not** a claim that the compiler runs on a GPU — see §0. + +--- + +## 0. What this is *not* (kill the over-claim up front) + +- **NOT "run the resolver/interpreter on a GPU."** A tree-walking resolver maximizes *both* SIMT anti-patterns at once: control divergence (every `Node` variant is a different `match` arm) and memory divergence (every child is a separate `Rc` at an arbitrary heap address). That workload belongs on a multicore CPU work-stealing scheduler; the CI-wall thesis already establishes the real lever is incrementality + caching, which is latency-bound, not FLOP-bound. GPU does nothing for it. +- **NOT opcode-bucketing scattered scalars.** SIMT width must come from *data-parallelism inside a node* (one op over a contiguous array), not *task-parallelism across nodes* (gathering scattered scalar ops by opcode — the gather/scatter is itself the pointer-chasing you were trying to escape, and the arithmetic intensity is hopeless). +- **NOT a general "reshape arbitrary programs" control plane.** That is post-self-host research. This demo handles exactly one recognized class: **pure elementwise array folds.** + +## 1. The claim the demo proves (load-bearing) + +> A pure `.dag` elementwise-array subgraph can be lowered to a contiguous-layout, fused, data-parallel kernel; the result is **bit-identical to the scalar interpreter under a declared numerical contract**; and any subgraph outside the lowerable class is **refused** with a typed, located honesty diagnostic — never silently miscompiled. + +Three things an XLA/NVIDIA audience treats as *hard* and this gets *structurally*: + +1. **Fusion/layout as a verified, content-addressed, inspectable value with a free differential oracle.** In XLA, layout-assignment + fusion are C++ passes whose correctness is *tested*; silent fusion miscompiles are a known pain. Here the scalar interpreter **is** the spec, so the fused kernel is bit-identical-or-refuse by construction, and the lowering carries a `DecodeFidelity` boundary stating exactly where it is exact vs declines. +2. **A new backend is a *row*, not a backend team.** Medium-agnostic emit (§4/§7) means "support this accelerator" = author a target row in `extdeps/languages//`, not fork a codegen. The optional GPU run is the proof: *same plan, one target row changed.* +3. **The schedule/layout is data, so auto-tuning can't miscompile.** The plan is a first-class `RealizationPlan` value and every rewrite is provably semantics-preserving (purity + explicit `EffectShape`), so searching over layouts is guaranteed meaning-preserving. + +## 2. On-model framing — first live consumer of the inert placement carriers + +The substrate **already models** the vocabulary; the roadmap (Ergonomics LANE) flags `Placement` / `Materialization` / `RealizationObjective` as *inert (no live consumer)* — the keystone inert-abstraction-lens's first RED witness. This demo makes them **load-bearing** by being their first real consumer: + +- `std/realization.dag`: `Placement = LocalInProcess | LocalFilesystem | RemoteNetwork`, `Materialization = Recompute | Memoize | Share`, `RealizedStep { shape, placement, materialization }`, `DecodeFidelity`, `RealizationPlan`, `RealizationObjective`. +- `std/realization_schedule.dag`: `RealizationPlan`, `Runnable`, `Schedule = List>`, cost accounting. +- `product/placement_supply.dag`: `PlacementSupplyRow` (host capacity) — literally "shaping for **supply**." + +The demo's substrate delta is therefore **minimal** (net concepts must not grow by re-invention, DESIGN §2): + +- **+1 `Placement` variant** for an accelerator/device-bound kernel (e.g. `LocalAccelerator`). A SIMT target is "one concept, every breadth" (§2-horizontal) — a new *placement*, not a new scheduler. +- **+1 `extdeps/languages//` target row** for kernel emit (sits beside `rust`, `go`, `typescript`, `python`), consumed by the existing `target_model_edge_translation_rules` fold — **N rows, not N×M emitters** (§4). +- **+1 numerical contract** on the plan (rounding-mode / FMA-contraction policy) — the float-exactness honesty boundary (§5/§4 `DecodeFidelity`). + +Everything else is *consumption* of existing carriers. + +## 3. The round trip (one fixture, runs in <60s) + +Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). Three ops so the demo shows **fusion**, not a single kernel. + +| Station | What it shows | Substrate | +|---|---|---| +| 1. source `.dag` → core graph | pure `Node`+`Edge`, `EffectShape = pure` — the precondition that *licenses* everything | `std/effects.dag`, ingest fold | +| 2. recognize + plan ("shaping for supply") | the elementwise-array-fold subgraph → a `RealizationPlan` value: contiguous SoA buffers, 3 ops fused into one pass, `placement: LocalAccelerator`. **Inspectable, printed.** | `std/realization.dag`, `std/realization_schedule.dag` (first live consumer) | +| 3. lower → fused kernel (forward fold) | the *same* translate fold run backward → one fused contiguous-loop / SIMD kernel | `target_model` translate + new `extdeps/languages/` row | +| 4. differential vs oracle | scalar interpreter on same input = ground truth; assert match on a discriminating input | existing v2 interpreter | +| 5. fail-closed arm | feed a non-elementwise / effectful subgraph (data-dependent gather, or carries an effect) → **typed located `DecodeFidelity` refusal**, no silent fallback | `std/realization.dag` `DecodeFidelity` | + +## 4. Acceptance bars (this is what makes it credible to *that* audience) + +- **Integer fixture → bit-exact.** Unarguable; no rounding ambiguity. (Demo v1, primary witness.) +- **Float fixture → exact under a *declared numerical contract*.** An XLA person will immediately object "fusing `a*b+c` into an FMA changes the rounding — your bit-identity is a lie." We get ahead of it: the plan carries an explicit **numerical contract** (rounding mode / FMA-contraction allowed?), the differential holds *under that declared contract*, and a fusion that would change rounding is **refused unless the contract permits it.** This is the `--xla_allow_excess_precision` / contraction-flag headache made into a *typed property on the plan* instead of a global flag. **Single most credible artifact to this audience — include in v1.** +- **Refusal arm is non-vacuous.** The fail-closed station must fire on a real discriminating input (a subgraph that *looks* lowerable but isn't), not a strawman. + +## 5. Do we need a real GPU? + +**No — not for confidence, and say so in the room as a strength.** The novel claim is the *seam* (verified layout/fusion + free oracle + typed honesty boundary incl. numerics). The CPU-SIMD/contiguous-loop differential + the refusal arm + the inspectable plan **is** the substance. A GPU run adds zero evidence to that claim — it only demonstrates medium-agnosticism (claim #2 of §1). + +- **Build the seam on CPU** (contiguous loop / SIMD). This is the architecturally interesting, fully-buildable-today part. +- **Keep "same plan, one target row → GPU" as an optional 60-second closer** on the operator's local device (SPIR-V via `wgpu`, or CUDA). Rhetorically powerful, epistemically a footnote — and *that framing itself* ("we don't need the GPU to trust the lowering — that's the point") is the pitch. + +## 6. Sequencing — seam first, silicon last + +1. **Modeling lane** — `+LocalAccelerator` placement variant; the recognizer's output as a `RealizationPlan`; the `NumericalContract` type + its `DecodeFidelity` coupling; the refusal diagnostic. All in `std/` + `extdeps/languages//`. Lands consumed-or-marked (Ergonomics-lane "wire the seams" rule). +2. **Execution lane** — the recognizer pass (elementwise-array-fold detection over the core graph) + the SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter; the differential harness; the **integer bit-exact witness** + the **refusal witness**, green-by-execution with a red-on-revert discriminator. +3. **Numerical-contract bar** — float fixture under declared contract; refuse-on-contraction-violation witness. +4. **GPU epilogue (optional, staged)** — swap the target row to a GPU backend on the operator's device; same bit-identity bar. + +## 7. Honesty line (prototype vs aspirational) + +- **Real today** (current v2 Rust interpreter, pre-self-host): the recognizer, the SoA fused-kernel handler, the differential + numerical-contract harness, the refusal arm, integer-bit-exact + float-under-contract bars. A runnable prototype, honestly labeled. +- **Aspirational / post-self-host**: the plan being *fully* substrate-native end-to-end, and reshaping *arbitrary* programs (vs the recognized elementwise class). For the demo the plan is a real modeled value even where some lowering is Rust-side; each prototype-Rust seam is marked so the pitch never overclaims. + +## Open threads + +- Exact spelling of the accelerator `Placement` variant (device-parameterized `LocalAccelerator` vs flat) — DFS the concept DAG before minting; a device is plausibly a `Vendor`-adjacent entity (DESIGN §3), not a fresh enum. +- Whether the numerical contract is a new std type or a refinement of an existing `float.dag` / `approximate_field.dag` carrier (reuse-first). +- Does the recognizer belong as a lens (read-only over the `Node` tree) or a translate-stage pass? (Lens-first per §6, unless it must produce the plan as part of lowering.) + + From d37aa6fcb14651aaeb3cf0d5b0eac51a1c86b51e Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 21:27:44 +0000 Subject: [PATCH 02/14] Add accelerator-kernel demo tangent lane to roadmap + charter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Operator-directed showcase: prove the daglang architecture to an accelerator/array-compiler audience (XLA/NVIDIA) in their own terms — fusion, layout assignment, numerical-semantics preservation. One recognized class (pure elementwise array folds); first live consumer of the inert Placement/Materialization/RealizationObjective carriers. - docs/plans/accelerator-demo-roundtrip.md — round-trip charter - roadmap_authority.dag — section_accelerator_demo_lane() - ROADMAP.md — regenerated from the authority (drift-gate clean) Co-Authored-By: Claude Opus 4.8 (1M context) --- ROADMAP.md | 22 ++++++++++++++++++++++ dsl/gunbc/roadmap_authority.dag | 32 +++++++++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) diff --git a/ROADMAP.md b/ROADMAP.md index 6513863388b..37455a12738 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -260,6 +260,28 @@ Depends on §6 — react/html is a first-class medium (idea-machine.md §3/§4), - [ ] react/html rendering stands up (real page, not fixture) — **SERVE page green-by-execution via gunbc-run landed (#5662); real socket the remaining gap (Lane C)** - [ ] add to the demo alongside the TypeScript emit (website + language, dogfoodable) +## ✦ Accelerator-kernel demo TANGENT — show the daglang moat in XLA's terms *(expansion · showcase · operator-directed)* + +→ [charter: the round-trip](docs/plans/accelerator-demo-roundtrip.md) + +A *small, honest subset* chosen because it is the easiest slice to communicate to an accelerator/array-compiler audience (NVIDIA / the XLA team) **in their own vocabulary** — fusion, layout assignment, buffer assignment, numerical-semantics preservation. **Displaced cost (§6): "the architecture is powerful but I can't show it to a hardware/compiler audience in 60 seconds."** NOT "run the compiler on a GPU" (a tree-walk maximizes both SIMT anti-patterns — control + memory divergence; that's a CPU scheduler workload). NOT opcode-bucketing (SIMT width comes from data-parallelism *inside* a node, not task-parallelism *across* nodes). One recognized class only: **pure elementwise array folds.** + +**On-model framing — first live consumer of the inert placement carriers.** The substrate already models `Placement`/`Materialization`/`RealizationObjective` (the Ergonomics-lane inert-lens's first RED witness); this lane makes them load-bearing. Net substrate delta is minimal (DESIGN §2): **+1 `Placement` variant** (accelerator, "one concept every breadth"), **+1 `extdeps/languages//` target row** (kernel emit via the existing translate fold — N rows not N×M), **+1 numerical contract** on the plan (the float-exactness `DecodeFidelity` boundary). Everything else is *consumption* of existing carriers. + +**◆ Milestones:** recognizer + `RealizationPlan` value (shaping for supply) → fused SoA kernel handler (CPU) + **integer bit-exact differential vs the scalar interpreter oracle** → **float exact under a declared numerical contract** (refuse-on-contraction-violation) → fail-closed refusal arm (non-elementwise/effectful → typed located `DecodeFidelity`) → *(optional epilogue)* same plan, one target row → GPU on operator device + +**Seam first (buildable today on the v2 interpreter — proves the claim without silicon):** + +- [ ] **modeling lane** — `+LocalAccelerator` `Placement` variant · recognizer output as a `RealizationPlan` value · `NumericalContract` type + its `DecodeFidelity` coupling · the refusal diagnostic. In `std/` + `extdeps/languages//`; lands consumed-or-marked. DFS the concept DAG before minting the device/contract types (reuse-first — a device is plausibly `Vendor`-adjacent, the contract plausibly a `float.dag`/`approximate_field.dag` refinement). [plan](docs/plans/accelerator-demo-roundtrip.md) +- [ ] **execution lane** — elementwise-array-fold recognizer pass over the core graph · SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter · differential harness · **integer bit-exact witness** + **refusal witness**, green-by-execution with a red-on-revert discriminator. [plan](docs/plans/accelerator-demo-roundtrip.md) +- [ ] **numerical-contract bar** *(most credible artifact to this audience — include in v1)* — float fixture exact under a declared rounding/FMA-contraction contract; a fusion that would change rounding is **refused unless the contract permits it** (the `--xla_allow_excess_precision` headache as a typed property, not a global flag). [plan](docs/plans/accelerator-demo-roundtrip.md) + +**Silicon last (optional — proves medium-agnosticism, not the seam):** + +- [ ] **GPU epilogue** — swap the target row to a GPU backend (SPIR-V via `wgpu`, or CUDA) on the operator's local device; same bit-identity bar. Epistemically a footnote — *"we don't need the GPU to trust the lowering, that's the point"* — but rhetorically the closer. [plan](docs/plans/accelerator-demo-roundtrip.md) + +**Pairs with:** Ergonomics LANE (first live consumer of the inert `Placement`/`Materialization`/`RealizationObjective` carriers) · §5 self-host (emit is the same fold, both directions) · §7 demo (a second sellable showcase beside the TS/website emit). + ## 8. Session dashboard on `.dag` (SHELVED) Product/infra tooling — shelved during the stability window (no `.dag`-correctness leverage right now). **One slice un-shelved (operator-directed): the roadmap-as-spawner MVP below** — it earns `.dag`-correctness leverage by making the roadmap the single authority for tracked work (§3) and is the first inhabitant of migrating ctrl onto the substrate (§7). diff --git a/dsl/gunbc/roadmap_authority.dag b/dsl/gunbc/roadmap_authority.dag index 07f79e1f864..414c45408bf 100644 --- a/dsl/gunbc/roadmap_authority.dag +++ b/dsl/gunbc/roadmap_authority.dag @@ -480,13 +480,43 @@ fn section_ergonomics_lane() -> RoadmapSection { } } +fn section_accelerator_demo_lane() -> RoadmapSection { + RoadmapSection { + title: "✦ Accelerator-kernel demo TANGENT — show the daglang moat in XLA's terms *(expansion · showcase · operator-directed)*", + elements: [ + section_prose(content: "→ [charter: the round-trip](docs/plans/accelerator-demo-roundtrip.md)"), + section_prose(content: "A *small, honest subset* chosen because it is the easiest slice to communicate to an accelerator/array-compiler audience (NVIDIA / the XLA team) **in their own vocabulary** — fusion, layout assignment, buffer assignment, numerical-semantics preservation. **Displaced cost (§6): \"the architecture is powerful but I can't show it to a hardware/compiler audience in 60 seconds.\"** NOT \"run the compiler on a GPU\" (a tree-walk maximizes both SIMT anti-patterns — control + memory divergence; that's a CPU scheduler workload). NOT opcode-bucketing (SIMT width comes from data-parallelism *inside* a node, not task-parallelism *across* nodes). One recognized class only: **pure elementwise array folds.**"), + section_prose(content: "**On-model framing — first live consumer of the inert placement carriers.** The substrate already models `Placement`/`Materialization`/`RealizationObjective` (the Ergonomics-lane inert-lens's first RED witness); this lane makes them load-bearing. Net substrate delta is minimal (DESIGN §2): **+1 `Placement` variant** (accelerator, \"one concept every breadth\"), **+1 `extdeps/languages//` target row** (kernel emit via the existing translate fold — N rows not N×M), **+1 numerical contract** on the plan (the float-exactness `DecodeFidelity` boundary). Everything else is *consumption* of existing carriers."), + section_prose(content: "**◆ Milestones:** recognizer + `RealizationPlan` value (shaping for supply) → fused SoA kernel handler (CPU) + **integer bit-exact differential vs the scalar interpreter oracle** → **float exact under a declared numerical contract** (refuse-on-contraction-violation) → fail-closed refusal arm (non-elementwise/effectful → typed located `DecodeFidelity`) → *(optional epilogue)* same plan, one target row → GPU on operator device"), + section_group( + label: "Seam first (buildable today on the v2 interpreter — proves the claim without silicon)", + nodes: [ + authored_doc(id: "accel-model", done: false, content: "**modeling lane** — `+LocalAccelerator` `Placement` variant · recognizer output as a `RealizationPlan` value · `NumericalContract` type + its `DecodeFidelity` coupling · the refusal diagnostic. In `std/` + `extdeps/languages//`; lands consumed-or-marked. DFS the concept DAG before minting the device/contract types (reuse-first — a device is plausibly `Vendor`-adjacent, the contract plausibly a `float.dag`/`approximate_field.dag` refinement).", path: "docs/plans/accelerator-demo-roundtrip.md"), + authored_doc(id: "accel-exec", done: false, content: "**execution lane** — elementwise-array-fold recognizer pass over the core graph · SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter · differential harness · **integer bit-exact witness** + **refusal witness**, green-by-execution with a red-on-revert discriminator.", path: "docs/plans/accelerator-demo-roundtrip.md"), + authored_doc(id: "accel-numeric", done: false, content: "**numerical-contract bar** *(most credible artifact to this audience — include in v1)* — float fixture exact under a declared rounding/FMA-contraction contract; a fusion that would change rounding is **refused unless the contract permits it** (the `--xla_allow_excess_precision` headache as a typed property, not a global flag).", path: "docs/plans/accelerator-demo-roundtrip.md"), + ], + edges: [], + ), + section_group( + label: "Silicon last (optional — proves medium-agnosticism, not the seam)", + nodes: [ + authored_doc(id: "accel-gpu", done: false, content: "**GPU epilogue** — swap the target row to a GPU backend (SPIR-V via `wgpu`, or CUDA) on the operator's local device; same bit-identity bar. Epistemically a footnote — *\"we don't need the GPU to trust the lowering, that's the point\"* — but rhetorically the closer.", path: "docs/plans/accelerator-demo-roundtrip.md"), + ], + edges: [], + ), + section_prose(content: "**Pairs with:** Ergonomics LANE (first live consumer of the inert `Placement`/`Materialization`/`RealizationObjective` carriers) · §5 self-host (emit is the same fold, both directions) · §7 demo (a second sellable showcase beside the TS/website emit)."), + ], + } +} + fn roadmap_authority() -> RoadmapDocument { RoadmapDocument { preamble: preamble(), lead_lanes: [section_ergonomics_lane()], sections: [ section_0(), section_1(), section_2(), section_3(), - section_4(), section_5(), section_6(), section_7(), section_8(), + section_4(), section_5(), section_6(), section_7(), + section_accelerator_demo_lane(), section_8(), ], } } From b462bd60c635c22884b05e62875e9d158fc2791d Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 21:32:07 +0000 Subject: [PATCH 03/14] Remove stray tool-call XML artifacts from charter doc EOF (cursor review #5969) Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 2 -- 1 file changed, 2 deletions(-) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 5ec110a1f26..5fe64367cc3 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -81,5 +81,3 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). - Exact spelling of the accelerator `Placement` variant (device-parameterized `LocalAccelerator` vs flat) — DFS the concept DAG before minting; a device is plausibly a `Vendor`-adjacent entity (DESIGN §3), not a fresh enum. - Whether the numerical contract is a new std type or a refinement of an existing `float.dag` / `approximate_field.dag` carrier (reuse-first). - Does the recognizer belong as a lens (read-only over the `Node` tree) or a translate-stage pass? (Lens-first per §6, unless it must produce the plan as part of lowering.) - - From ae09b89b60616c773c50d9ac100dcfa311d7d937 Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 21:45:22 +0000 Subject: [PATCH 04/14] =?UTF-8?q?charter:=20add=20intuition=20section=20?= =?UTF-8?q?=E2=80=94=20arbitrary=20program=20DAG=20->=20numerical=20graph?= =?UTF-8?q?=20(operator=20request)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Plain-language bridge for how user programs relate to GPU/SIMT execution: task-DAG vs dataflow-DAG, where the numerical subgraph hides, shaping-for- supply as a provable layout choice, and the honest critical-path bound. Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 27 ++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 5fe64367cc3..7c706cbd3ca 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -13,6 +13,33 @@ This draft is downstream of [DESIGN.md](../../DESIGN.md) §4 (one grammar, both - **NOT opcode-bucketing scattered scalars.** SIMT width must come from *data-parallelism inside a node* (one op over a contiguous array), not *task-parallelism across nodes* (gathering scattered scalar ops by opcode — the gather/scatter is itself the pointer-chasing you were trying to escape, and the arithmetic intensity is hopeless). - **NOT a general "reshape arbitrary programs" control plane.** That is post-self-host research. This demo handles exactly one recognized class: **pure elementwise array folds.** +## 0.5. Intuition — how your programs relate to GPU execution (the shared language) + +The phrase to hold onto is **"arbitrary program DAG → numerical graph."** Your program is already a dependency graph; the accelerator wants a *particular kind* of dependency graph. The demo is the bridge that finds the second kind inside the first. + +**"DAG" alone does not pick the hardware — the *nodes* do.** Two programs can both be pure dependency graphs and belong on opposite chips: + +- A **task DAG** — coarse, *heterogeneous* nodes ("resolve this", "fold that"), wired by dependencies, scheduled dynamically. This is what a build system (Bazel) or a compiler pipeline is. → belongs on a **multicore CPU**: a handful of big, different jobs running in parallel across cores. +- A **dataflow / numerical DAG** — fine, *homogeneous* nodes (one arithmetic op applied across a whole array), static structure, no branching. This is what an ML graph (XLA's HLO, a tensor program) is. → belongs on a **GPU**. + +So the mental model for the two chips: + +| | CPU (MIMD) | GPU (SIMT) | +|---|---|---| +| What it wants | any mix of different instructions on demand | **one** instruction over a **big contiguous array** of data | +| Strength | heterogeneous, branchy, irregular work | thousands of identical, branch-free arithmetic ops | +| The bet | big caches + speculation absorb unpredictability | march thousands of lanes in lockstep, no caches needed | + +A GPU is essentially a **batch executor for arithmetic**: if at one moment you can hand it *one* operation over a million contiguous data elements, it's ideal; if you hand it a grab-bag of different operations on scattered data, it falls apart. Two things break the lockstep and collapse it back toward serial: **branches** (lanes want different instructions) and **scattered memory** (lanes want different addresses). That's why a tree-walking interpreter is the *worst* case — every node is a different `match` arm (branches) and every child is a random heap pointer (scattered memory). It maxes out both. + +**Where the GPU-friendly graph hides in your program.** The crucial move is that SIMT width comes from **data-parallelism *inside* a node** (one `map (+)` over a 10⁶-element array), **not** task-parallelism *across* nodes (gathering a million scattered scalar adds — the gathering is itself the scattered-memory problem you were trying to escape). So you don't "send the whole program to the GPU." You **recognize the subgraph that is already a numerical graph** — a chain of pure, elementwise, array-shaped ops like `relu(a*b + c)` — and lower *that* to a kernel. The rest of the program stays on the CPU. The accelerator gets the array math; the orchestration stays where orchestration belongs. + +**"Shaping for supply" — why daglang can do this and a normal language can't.** Whether your array data sits scattered across the heap or packed in one contiguous buffer is **not physics — it's a layout decision the compiler makes.** Today the naive choice (scattered) is what makes pointer-chasing look mandatory. Because the `.dag` *owns* lowering, it can instead *choose* a contiguous layout that turns latent-but-hidden data-parallelism into the coalesced, lockstep-friendly form the GPU wants. And because `.dag` programs are **pure with explicit effects**, that relayout is *provably* meaning-preserving — a normal language can't prove it safe because hidden side-effects might depend on the old order. That provable freedom to reshape layout is the moat; the GPU kernel is just the payoff. + +**The honest bound.** This reveals data-parallelism that layout was *hiding*; it cannot *manufacture* parallelism your data dependencies forbid. A serial chain (each step needs the last) has a hard floor — its critical path — that no layout beats. So the demo deliberately targets the one place the win is real (pure elementwise array folds) and is fail-closed everywhere else. + +So the one-sentence relationship: **your arbitrary program is a task DAG; inside it live numerical subgraphs; the demo recognizes one, chooses a layout that makes it SIMT-shaped, and lowers it — proving the recognition is semantics-exact or honestly refused.** + ## 1. The claim the demo proves (load-bearing) > A pure `.dag` elementwise-array subgraph can be lowered to a contiguous-layout, fused, data-parallel kernel; the result is **bit-identical to the scalar interpreter under a declared numerical contract**; and any subgraph outside the lowerable class is **refused** with a typed, located honesty diagnostic — never silently miscompiled. From 179845b0b33f8b768263484c947699b422920063 Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 21:55:26 +0000 Subject: [PATCH 05/14] WIP: gpu accelerated .dag --- docs/plans/accelerator-demo-roundtrip.md | 18 ++++++++++++++++++ dsl/gunbc/roadmap_authority.dag | 1 + 2 files changed, 19 insertions(+) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 7c706cbd3ca..7395a674904 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -50,6 +50,24 @@ Three things an XLA/NVIDIA audience treats as *hard* and this gets *structurally 2. **A new backend is a *row*, not a backend team.** Medium-agnostic emit (§4/§7) means "support this accelerator" = author a target row in `extdeps/languages//`, not fork a codegen. The optional GPU run is the proof: *same plan, one target row changed.* 3. **The schedule/layout is data, so auto-tuning can't miscompile.** The plan is a first-class `RealizationPlan` value and every rewrite is provably semantics-preserving (purity + explicit `EffectShape`), so searching over layouts is guaranteed meaning-preserving. +## 1.5. The relational projection — the demo artifact that is *for the author* (and doubles as the pitch) + +A first-class deliverable, not a debug print: the demo must **render the relationship** "arbitrary program DAG → numerical graph → kernel" as an inspectable artifact, because making that relationship legible is half the point (to the author, who thinks in array compilers; and to the audience, who thinks in HLO). The **recognize + plan** station's `RealizationPlan` value is *promoted from a side-effect to the product.* + +Shape — a **triptych** over one input program: + +| LEFT — your program | MIDDLE — the numerical graph inside it | RIGHT — the lowering | +|---|---|---| +| the program as written (the full **task DAG**) | the pure elementwise-array subgraph **lifted out**, shown as a **dataflow graph** — literally "arbitrary dag → numerical graph", the HLO-shaped view | the layout/fusion plan (SoA buffers, fused ops, `placement: LocalAccelerator`) + the **fidelity verdict** (Lossless / Lossy / Refused) | + +Why this is on-model, not scope creep: + +- It's a **lens** — read-only over the `Node` tree + the `RealizationPlan` value, storing nothing (DESIGN §6). A new analysis costs zero substrate edits. +- It elevates the project's own pitch point ("the schedule/layout is *data*, so it's inspectable and can't silently miscompile") from a claim into the **rendered artifact** that demonstrates it. +- Rendering is **"one more medium"** (§4/§7): a text / DOT structural projection first (provable, in-substrate), an HTML/React visual on top — *the same projected data, two media.* This **converges with §7** (the website/React rendering lane): the triptych is a natural candidate for the "demo beside the TS emit" milestone. + +Acceptance: the projection is *derived* from the same `RealizationPlan` the kernel is lowered from (single authority — the picture cannot drift from what actually executes), and the MIDDLE→RIGHT carving shows the exact subgraph that was lowered, with the refusal arm rendering a located refusal rather than a blank. + ## 2. On-model framing — first live consumer of the inert placement carriers The substrate **already models** the vocabulary; the roadmap (Ergonomics LANE) flags `Placement` / `Materialization` / `RealizationObjective` as *inert (no live consumer)* — the keystone inert-abstraction-lens's first RED witness. This demo makes them **load-bearing** by being their first real consumer: diff --git a/dsl/gunbc/roadmap_authority.dag b/dsl/gunbc/roadmap_authority.dag index 414c45408bf..8db33fabecc 100644 --- a/dsl/gunbc/roadmap_authority.dag +++ b/dsl/gunbc/roadmap_authority.dag @@ -494,6 +494,7 @@ fn section_accelerator_demo_lane() -> RoadmapSection { authored_doc(id: "accel-model", done: false, content: "**modeling lane** — `+LocalAccelerator` `Placement` variant · recognizer output as a `RealizationPlan` value · `NumericalContract` type + its `DecodeFidelity` coupling · the refusal diagnostic. In `std/` + `extdeps/languages//`; lands consumed-or-marked. DFS the concept DAG before minting the device/contract types (reuse-first — a device is plausibly `Vendor`-adjacent, the contract plausibly a `float.dag`/`approximate_field.dag` refinement).", path: "docs/plans/accelerator-demo-roundtrip.md"), authored_doc(id: "accel-exec", done: false, content: "**execution lane** — elementwise-array-fold recognizer pass over the core graph · SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter · differential harness · **integer bit-exact witness** + **refusal witness**, green-by-execution with a red-on-revert discriminator.", path: "docs/plans/accelerator-demo-roundtrip.md"), authored_doc(id: "accel-numeric", done: false, content: "**numerical-contract bar** *(most credible artifact to this audience — include in v1)* — float fixture exact under a declared rounding/FMA-contraction contract; a fusion that would change rounding is **refused unless the contract permits it** (the `--xla_allow_excess_precision` headache as a typed property, not a global flag).", path: "docs/plans/accelerator-demo-roundtrip.md"), + authored_doc(id: "accel-relational-projection", done: false, content: "**relational projection** *(first-class artifact — for the author and the pitch)* — render \"arbitrary program DAG → numerical graph → kernel\" as a triptych (your program · the elementwise-array subgraph lifted out as a dataflow/HLO-shaped graph · the layout/fusion plan + fidelity verdict). A **lens** over the `Node` tree + `RealizationPlan` (zero substrate edits), *derived* from the same plan the kernel lowers from (can't drift from what executes). Text/DOT projection first, HTML/React visual on top (\"one more medium\") — **converges with §7** as the demo-beside-the-TS-emit candidate.", path: "docs/plans/accelerator-demo-roundtrip.md"), ], edges: [], ), From b10cf6d43ea679406677a0c3a44c7a7686d24b69 Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 21:56:17 +0000 Subject: [PATCH 06/14] charter+lane: relational projection as first-class demo artifact + regen ROADMAP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Operator request: part of the demo must relate the author's work to GPU work as a first-class output, not plan prose. Adds the relational-projection triptych (program DAG -> numerical subgraph -> kernel plan + fidelity) as a lens-based deliverable; converges with the section 7 render lane. Regenerates ROADMAP.md to match the authority node (drift-gate clean — prior WIP commit moved the authority but not the rendered artifact). Co-Authored-By: Claude Opus 4.8 (1M context) --- ROADMAP.md | 1 + 1 file changed, 1 insertion(+) diff --git a/ROADMAP.md b/ROADMAP.md index 37455a12738..5708e15d27e 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -275,6 +275,7 @@ A *small, honest subset* chosen because it is the easiest slice to communicate t - [ ] **modeling lane** — `+LocalAccelerator` `Placement` variant · recognizer output as a `RealizationPlan` value · `NumericalContract` type + its `DecodeFidelity` coupling · the refusal diagnostic. In `std/` + `extdeps/languages//`; lands consumed-or-marked. DFS the concept DAG before minting the device/contract types (reuse-first — a device is plausibly `Vendor`-adjacent, the contract plausibly a `float.dag`/`approximate_field.dag` refinement). [plan](docs/plans/accelerator-demo-roundtrip.md) - [ ] **execution lane** — elementwise-array-fold recognizer pass over the core graph · SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter · differential harness · **integer bit-exact witness** + **refusal witness**, green-by-execution with a red-on-revert discriminator. [plan](docs/plans/accelerator-demo-roundtrip.md) - [ ] **numerical-contract bar** *(most credible artifact to this audience — include in v1)* — float fixture exact under a declared rounding/FMA-contraction contract; a fusion that would change rounding is **refused unless the contract permits it** (the `--xla_allow_excess_precision` headache as a typed property, not a global flag). [plan](docs/plans/accelerator-demo-roundtrip.md) +- [ ] **relational projection** *(first-class artifact — for the author and the pitch)* — render "arbitrary program DAG → numerical graph → kernel" as a triptych (your program · the elementwise-array subgraph lifted out as a dataflow/HLO-shaped graph · the layout/fusion plan + fidelity verdict). A **lens** over the `Node` tree + `RealizationPlan` (zero substrate edits), *derived* from the same plan the kernel lowers from (can't drift from what executes). Text/DOT projection first, HTML/React visual on top ("one more medium") — **converges with §7** as the demo-beside-the-TS-emit candidate. [plan](docs/plans/accelerator-demo-roundtrip.md) **Silicon last (optional — proves medium-agnosticism, not the seam):** From 7ed2a4b384e61d3e5d2540c59e2d9b1b59458c9f Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 22:01:33 +0000 Subject: [PATCH 07/14] Split #5969: drop roadmap-authority lane node (fold into #5968 reconciliation) De-conflict with #5968 (foundational owner+signoff rework of every RoadmapNode + wholesale ROADMAP.md regen). Two PRs regenerating the same generated authority is the merge-skew class we're killing. #5969 keeps the charter doc + relational- projection design only (no roadmap conflict); the tangent-lane node folds into #5968's content pass with owner=tidy-deer-560 + a closure condition. Co-Authored-By: Claude Opus 4.8 (1M context) --- ROADMAP.md | 23 ----------------------- dsl/gunbc/roadmap_authority.dag | 33 +-------------------------------- 2 files changed, 1 insertion(+), 55 deletions(-) diff --git a/ROADMAP.md b/ROADMAP.md index 5708e15d27e..6513863388b 100644 --- a/ROADMAP.md +++ b/ROADMAP.md @@ -260,29 +260,6 @@ Depends on §6 — react/html is a first-class medium (idea-machine.md §3/§4), - [ ] react/html rendering stands up (real page, not fixture) — **SERVE page green-by-execution via gunbc-run landed (#5662); real socket the remaining gap (Lane C)** - [ ] add to the demo alongside the TypeScript emit (website + language, dogfoodable) -## ✦ Accelerator-kernel demo TANGENT — show the daglang moat in XLA's terms *(expansion · showcase · operator-directed)* - -→ [charter: the round-trip](docs/plans/accelerator-demo-roundtrip.md) - -A *small, honest subset* chosen because it is the easiest slice to communicate to an accelerator/array-compiler audience (NVIDIA / the XLA team) **in their own vocabulary** — fusion, layout assignment, buffer assignment, numerical-semantics preservation. **Displaced cost (§6): "the architecture is powerful but I can't show it to a hardware/compiler audience in 60 seconds."** NOT "run the compiler on a GPU" (a tree-walk maximizes both SIMT anti-patterns — control + memory divergence; that's a CPU scheduler workload). NOT opcode-bucketing (SIMT width comes from data-parallelism *inside* a node, not task-parallelism *across* nodes). One recognized class only: **pure elementwise array folds.** - -**On-model framing — first live consumer of the inert placement carriers.** The substrate already models `Placement`/`Materialization`/`RealizationObjective` (the Ergonomics-lane inert-lens's first RED witness); this lane makes them load-bearing. Net substrate delta is minimal (DESIGN §2): **+1 `Placement` variant** (accelerator, "one concept every breadth"), **+1 `extdeps/languages//` target row** (kernel emit via the existing translate fold — N rows not N×M), **+1 numerical contract** on the plan (the float-exactness `DecodeFidelity` boundary). Everything else is *consumption* of existing carriers. - -**◆ Milestones:** recognizer + `RealizationPlan` value (shaping for supply) → fused SoA kernel handler (CPU) + **integer bit-exact differential vs the scalar interpreter oracle** → **float exact under a declared numerical contract** (refuse-on-contraction-violation) → fail-closed refusal arm (non-elementwise/effectful → typed located `DecodeFidelity`) → *(optional epilogue)* same plan, one target row → GPU on operator device - -**Seam first (buildable today on the v2 interpreter — proves the claim without silicon):** - -- [ ] **modeling lane** — `+LocalAccelerator` `Placement` variant · recognizer output as a `RealizationPlan` value · `NumericalContract` type + its `DecodeFidelity` coupling · the refusal diagnostic. In `std/` + `extdeps/languages//`; lands consumed-or-marked. DFS the concept DAG before minting the device/contract types (reuse-first — a device is plausibly `Vendor`-adjacent, the contract plausibly a `float.dag`/`approximate_field.dag` refinement). [plan](docs/plans/accelerator-demo-roundtrip.md) -- [ ] **execution lane** — elementwise-array-fold recognizer pass over the core graph · SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter · differential harness · **integer bit-exact witness** + **refusal witness**, green-by-execution with a red-on-revert discriminator. [plan](docs/plans/accelerator-demo-roundtrip.md) -- [ ] **numerical-contract bar** *(most credible artifact to this audience — include in v1)* — float fixture exact under a declared rounding/FMA-contraction contract; a fusion that would change rounding is **refused unless the contract permits it** (the `--xla_allow_excess_precision` headache as a typed property, not a global flag). [plan](docs/plans/accelerator-demo-roundtrip.md) -- [ ] **relational projection** *(first-class artifact — for the author and the pitch)* — render "arbitrary program DAG → numerical graph → kernel" as a triptych (your program · the elementwise-array subgraph lifted out as a dataflow/HLO-shaped graph · the layout/fusion plan + fidelity verdict). A **lens** over the `Node` tree + `RealizationPlan` (zero substrate edits), *derived* from the same plan the kernel lowers from (can't drift from what executes). Text/DOT projection first, HTML/React visual on top ("one more medium") — **converges with §7** as the demo-beside-the-TS-emit candidate. [plan](docs/plans/accelerator-demo-roundtrip.md) - -**Silicon last (optional — proves medium-agnosticism, not the seam):** - -- [ ] **GPU epilogue** — swap the target row to a GPU backend (SPIR-V via `wgpu`, or CUDA) on the operator's local device; same bit-identity bar. Epistemically a footnote — *"we don't need the GPU to trust the lowering, that's the point"* — but rhetorically the closer. [plan](docs/plans/accelerator-demo-roundtrip.md) - -**Pairs with:** Ergonomics LANE (first live consumer of the inert `Placement`/`Materialization`/`RealizationObjective` carriers) · §5 self-host (emit is the same fold, both directions) · §7 demo (a second sellable showcase beside the TS/website emit). - ## 8. Session dashboard on `.dag` (SHELVED) Product/infra tooling — shelved during the stability window (no `.dag`-correctness leverage right now). **One slice un-shelved (operator-directed): the roadmap-as-spawner MVP below** — it earns `.dag`-correctness leverage by making the roadmap the single authority for tracked work (§3) and is the first inhabitant of migrating ctrl onto the substrate (§7). diff --git a/dsl/gunbc/roadmap_authority.dag b/dsl/gunbc/roadmap_authority.dag index 8db33fabecc..07f79e1f864 100644 --- a/dsl/gunbc/roadmap_authority.dag +++ b/dsl/gunbc/roadmap_authority.dag @@ -480,44 +480,13 @@ fn section_ergonomics_lane() -> RoadmapSection { } } -fn section_accelerator_demo_lane() -> RoadmapSection { - RoadmapSection { - title: "✦ Accelerator-kernel demo TANGENT — show the daglang moat in XLA's terms *(expansion · showcase · operator-directed)*", - elements: [ - section_prose(content: "→ [charter: the round-trip](docs/plans/accelerator-demo-roundtrip.md)"), - section_prose(content: "A *small, honest subset* chosen because it is the easiest slice to communicate to an accelerator/array-compiler audience (NVIDIA / the XLA team) **in their own vocabulary** — fusion, layout assignment, buffer assignment, numerical-semantics preservation. **Displaced cost (§6): \"the architecture is powerful but I can't show it to a hardware/compiler audience in 60 seconds.\"** NOT \"run the compiler on a GPU\" (a tree-walk maximizes both SIMT anti-patterns — control + memory divergence; that's a CPU scheduler workload). NOT opcode-bucketing (SIMT width comes from data-parallelism *inside* a node, not task-parallelism *across* nodes). One recognized class only: **pure elementwise array folds.**"), - section_prose(content: "**On-model framing — first live consumer of the inert placement carriers.** The substrate already models `Placement`/`Materialization`/`RealizationObjective` (the Ergonomics-lane inert-lens's first RED witness); this lane makes them load-bearing. Net substrate delta is minimal (DESIGN §2): **+1 `Placement` variant** (accelerator, \"one concept every breadth\"), **+1 `extdeps/languages//` target row** (kernel emit via the existing translate fold — N rows not N×M), **+1 numerical contract** on the plan (the float-exactness `DecodeFidelity` boundary). Everything else is *consumption* of existing carriers."), - section_prose(content: "**◆ Milestones:** recognizer + `RealizationPlan` value (shaping for supply) → fused SoA kernel handler (CPU) + **integer bit-exact differential vs the scalar interpreter oracle** → **float exact under a declared numerical contract** (refuse-on-contraction-violation) → fail-closed refusal arm (non-elementwise/effectful → typed located `DecodeFidelity`) → *(optional epilogue)* same plan, one target row → GPU on operator device"), - section_group( - label: "Seam first (buildable today on the v2 interpreter — proves the claim without silicon)", - nodes: [ - authored_doc(id: "accel-model", done: false, content: "**modeling lane** — `+LocalAccelerator` `Placement` variant · recognizer output as a `RealizationPlan` value · `NumericalContract` type + its `DecodeFidelity` coupling · the refusal diagnostic. In `std/` + `extdeps/languages//`; lands consumed-or-marked. DFS the concept DAG before minting the device/contract types (reuse-first — a device is plausibly `Vendor`-adjacent, the contract plausibly a `float.dag`/`approximate_field.dag` refinement).", path: "docs/plans/accelerator-demo-roundtrip.md"), - authored_doc(id: "accel-exec", done: false, content: "**execution lane** — elementwise-array-fold recognizer pass over the core graph · SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter · differential harness · **integer bit-exact witness** + **refusal witness**, green-by-execution with a red-on-revert discriminator.", path: "docs/plans/accelerator-demo-roundtrip.md"), - authored_doc(id: "accel-numeric", done: false, content: "**numerical-contract bar** *(most credible artifact to this audience — include in v1)* — float fixture exact under a declared rounding/FMA-contraction contract; a fusion that would change rounding is **refused unless the contract permits it** (the `--xla_allow_excess_precision` headache as a typed property, not a global flag).", path: "docs/plans/accelerator-demo-roundtrip.md"), - authored_doc(id: "accel-relational-projection", done: false, content: "**relational projection** *(first-class artifact — for the author and the pitch)* — render \"arbitrary program DAG → numerical graph → kernel\" as a triptych (your program · the elementwise-array subgraph lifted out as a dataflow/HLO-shaped graph · the layout/fusion plan + fidelity verdict). A **lens** over the `Node` tree + `RealizationPlan` (zero substrate edits), *derived* from the same plan the kernel lowers from (can't drift from what executes). Text/DOT projection first, HTML/React visual on top (\"one more medium\") — **converges with §7** as the demo-beside-the-TS-emit candidate.", path: "docs/plans/accelerator-demo-roundtrip.md"), - ], - edges: [], - ), - section_group( - label: "Silicon last (optional — proves medium-agnosticism, not the seam)", - nodes: [ - authored_doc(id: "accel-gpu", done: false, content: "**GPU epilogue** — swap the target row to a GPU backend (SPIR-V via `wgpu`, or CUDA) on the operator's local device; same bit-identity bar. Epistemically a footnote — *\"we don't need the GPU to trust the lowering, that's the point\"* — but rhetorically the closer.", path: "docs/plans/accelerator-demo-roundtrip.md"), - ], - edges: [], - ), - section_prose(content: "**Pairs with:** Ergonomics LANE (first live consumer of the inert `Placement`/`Materialization`/`RealizationObjective` carriers) · §5 self-host (emit is the same fold, both directions) · §7 demo (a second sellable showcase beside the TS/website emit)."), - ], - } -} - fn roadmap_authority() -> RoadmapDocument { RoadmapDocument { preamble: preamble(), lead_lanes: [section_ergonomics_lane()], sections: [ section_0(), section_1(), section_2(), section_3(), - section_4(), section_5(), section_6(), section_7(), - section_accelerator_demo_lane(), section_8(), + section_4(), section_5(), section_6(), section_7(), section_8(), ], } } From 5969288b79ef0a6f902b40f7acbb877a8e997adb Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 22:13:08 +0000 Subject: [PATCH 08/14] WIP: gpu accelerated .dag --- docs/plans/accelerator-demo-roundtrip.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 7395a674904..092c9b35fff 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -70,9 +70,10 @@ Acceptance: the projection is *derived* from the same `RealizationPlan` the kern ## 2. On-model framing — first live consumer of the inert placement carriers -The substrate **already models** the vocabulary; the roadmap (Ergonomics LANE) flags `Placement` / `Materialization` / `RealizationObjective` as *inert (no live consumer)* — the keystone inert-abstraction-lens's first RED witness. This demo makes them **load-bearing** by being their first real consumer: +The substrate **already models** the vocabulary; the roadmap (Ergonomics LANE) flags **`Placement` / `Materialization`** as *still inert (no live consumer)* — part of the keystone inert-abstraction-lens's RED set. (`RealizationObjective` / `realization_width` are **already wired** via `ci_floor_plan` — `inert_layer_lens.dag` records the schedule/width arm as live; do **not** treat that arm as greenfield.) This demo makes the *placement/materialization* arm **load-bearing** by being its first real consumer: -- `std/realization.dag`: `Placement = LocalInProcess | LocalFilesystem | RemoteNetwork`, `Materialization = Recompute | Memoize | Share`, `RealizedStep { shape, placement, materialization }`, `DecodeFidelity`, `RealizationPlan`, `RealizationObjective`. +- `std/realization.dag`: `Placement = LocalInProcess | LocalFilesystem | RemoteNetwork`, `Materialization = Recompute | Memoize | Share`, `RealizedStep { shape, placement, materialization }`, `RealizationPlan`, `RealizationObjective`. +- `extdeps/communication/medium.dag`: `DecodeFidelity = Lossless | Lossy` (the honesty-boundary type — declared here, an extdeps-layer type, *not* in std; consume it, never re-fork it). - `std/realization_schedule.dag`: `RealizationPlan`, `Runnable`, `Schedule = List>`, cost accounting. - `product/placement_supply.dag`: `PlacementSupplyRow` (host capacity) — literally "shaping for **supply**." @@ -94,7 +95,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). | 2. recognize + plan ("shaping for supply") | the elementwise-array-fold subgraph → a `RealizationPlan` value: contiguous SoA buffers, 3 ops fused into one pass, `placement: LocalAccelerator`. **Inspectable, printed.** | `std/realization.dag`, `std/realization_schedule.dag` (first live consumer) | | 3. lower → fused kernel (forward fold) | the *same* translate fold run backward → one fused contiguous-loop / SIMD kernel | `target_model` translate + new `extdeps/languages/` row | | 4. differential vs oracle | scalar interpreter on same input = ground truth; assert match on a discriminating input | existing v2 interpreter | -| 5. fail-closed arm | feed a non-elementwise / effectful subgraph (data-dependent gather, or carries an effect) → **typed located `DecodeFidelity` refusal**, no silent fallback | `std/realization.dag` `DecodeFidelity` | +| 5. fail-closed arm | feed a non-elementwise / effectful subgraph (data-dependent gather, or carries an effect) → **typed located `DecodeFidelity` refusal**, no silent fallback | `extdeps/communication/medium.dag` `DecodeFidelity` | ## 4. Acceptance bars (this is what makes it credible to *that* audience) From 9b628750fbe3d80ae1eaa19f450fd5a0a3eccfde Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 22:13:21 +0000 Subject: [PATCH 09/14] charter fixes (cursor #5969): DecodeFidelity home, narrow inert claim, hand-Rust scaffold receipt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit F1: DecodeFidelity is declared in extdeps/communication/medium.dag, not std/realization.dag — fix the cite (consume-never-fork, DESIGN §3). F2: RealizationObjective/realization_width are already wired via ci_floor_plan (inert_layer_lens.dag) — narrow the 'first consumer' claim to Placement/Materialization only. F3: name the execution-lane Rust as scaffold with explicit per-component dissolution triggers + the accel-exec tracking row (DESIGN §7 anti-cement; no census ratchet pressure). Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 092c9b35fff..f3bd27e9f43 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -122,6 +122,14 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). - **Real today** (current v2 Rust interpreter, pre-self-host): the recognizer, the SoA fused-kernel handler, the differential + numerical-contract harness, the refusal arm, integer-bit-exact + float-under-contract bars. A runnable prototype, honestly labeled. - **Aspirational / post-self-host**: the plan being *fully* substrate-native end-to-end, and reshaping *arbitrary* programs (vs the recognized elementwise class). For the demo the plan is a real modeled value even where some lowering is Rust-side; each prototype-Rust seam is marked so the pitch never overclaims. +**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** Each lands with a named **dissolution trigger** and is tracked by the `accel-exec` roadmap row (owner `tidy-deer-560`, folded into #5968), which does not flip `[x]` until the dissolution is either done or re-deferred with a reason: + + - *recognizer* → dissolves into a `.dag` **lens** (read-only over the `Node` tree) once the lens can express the elementwise-fold predicate; dissolution trigger `feature:dag-elementwise-recognizer-lens`. + - *SoA fused-kernel handler* → dissolves into a `.dag` **Realization handler** bound to the `extdeps/languages/` target row (emit is the same fold, both directions); trigger `feature:dag-kernel-realization-handler`. + - *differential harness* → dissolves into a `.dag` **witness** (the scalar interpreter is already the in-substrate oracle); trigger `feature:dag-differential-witness`. + + Until then they are `🟡`-marked prototype Rust on the doomed seed — they add **no** census ratchet pressure and must not be cemented into emit templates (DESIGN §7; the anti-cement rule). Net Rust delta is bounded and has a written path to zero; it is not new permanent compiler surface. + ## Open threads - Exact spelling of the accelerator `Placement` variant (device-parameterized `LocalAccelerator` vs flat) — DFS the concept DAG before minting; a device is plausibly a `Vendor`-adjacent entity (DESIGN §3), not a fresh enum. From 01104e9e2d1840fe3782ffeddd7dca66369cd7c3 Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 22:29:49 +0000 Subject: [PATCH 10/14] WIP: gpu accelerated .dag --- docs/plans/accelerator-demo-roundtrip.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index f3bd27e9f43..3827f04335e 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -122,7 +122,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). - **Real today** (current v2 Rust interpreter, pre-self-host): the recognizer, the SoA fused-kernel handler, the differential + numerical-contract harness, the refusal arm, integer-bit-exact + float-under-contract bars. A runnable prototype, honestly labeled. - **Aspirational / post-self-host**: the plan being *fully* substrate-native end-to-end, and reshaping *arbitrary* programs (vs the recognized elementwise class). For the demo the plan is a real modeled value even where some lowering is Rust-side; each prototype-Rust seam is marked so the pitch never overclaims. -**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** Each lands with a named **dissolution trigger** and is tracked by the `accel-exec` roadmap row (owner `tidy-deer-560`, folded into #5968), which does not flip `[x]` until the dissolution is either done or re-deferred with a reason: +**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored in the roadmap reconciliation (#5968), and this charter is sequenced to merge **after** that row exists on main (which also provides this doc's inbound ROADMAP link — see the note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: - *recognizer* → dissolves into a `.dag` **lens** (read-only over the `Node` tree) once the lens can express the elementwise-fold predicate; dissolution trigger `feature:dag-elementwise-recognizer-lens`. - *SoA fused-kernel handler* → dissolves into a `.dag` **Realization handler** bound to the `extdeps/languages/` target row (emit is the same fold, both directions); trigger `feature:dag-kernel-realization-handler`. From 0d14123249ef1a446cff5a784cd6e1f84aa6064c Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 22:30:01 +0000 Subject: [PATCH 11/14] charter (cursor #5969 F2 + sequencing): self-contained dissolution authority; document PR ordering after #5968 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit F2: the dissolution-trigger authority is the charter itself (self-contained), not a not-yet-existing roadmap row; accel-exec is the tracking row in #5968, and this doc is sequenced to merge after #5968 (which provides the inbound link + the row). F1 (orphan): resolved by sequencing — the inbound ROADMAP link lives in #5968's node (single authority for the generated roadmap; kept out of this PR to avoid collision). Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 3827f04335e..a22eee714cc 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -112,6 +112,8 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). ## 6. Sequencing — seam first, silicon last +> **PR sequencing note.** This charter doc and its inbound ROADMAP link are one unit (the live doc-graph wall, `doc_reachability_project.rs`, fails on an orphan doc). The linking roadmap node (`accel-*`, incl. `accel-exec`) is authored in the roadmap-authority reconciliation **#5968** (single authority for the generated roadmap — kept out of this PR to avoid a generated-artifact merge collision). So this doc PR merges **after #5968 lands**; at that point the inbound link and the tracking rows are on main and the doc is reachable. Until then this PR is held (draft). + 1. **Modeling lane** — `+LocalAccelerator` placement variant; the recognizer's output as a `RealizationPlan`; the `NumericalContract` type + its `DecodeFidelity` coupling; the refusal diagnostic. All in `std/` + `extdeps/languages//`. Lands consumed-or-marked (Ergonomics-lane "wire the seams" rule). 2. **Execution lane** — the recognizer pass (elementwise-array-fold detection over the core graph) + the SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter; the differential harness; the **integer bit-exact witness** + the **refusal witness**, green-by-execution with a red-on-revert discriminator. 3. **Numerical-contract bar** — float fixture under declared contract; refuse-on-contraction-violation witness. From 7351d93473cd8bf0e8265f16bf5b09579a055782 Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 22:32:07 +0000 Subject: [PATCH 12/14] =?UTF-8?q?charter:=20correct=20sequencing=20ref=20?= =?UTF-8?q?=E2=80=94=20link=20lands=20in=20loyal-bee=20content=20slice,=20?= =?UTF-8?q?not=20#5968=20mechanism=20PR?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Per loyal-bee-794: #5968 is mechanism-only (closure semantics); the accel node + doc pointer + accel-exec row land in their decision-independent early content slice. #5969 rebases on that slice (not #5968) to clear the orphan witness. Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index a22eee714cc..baffb69105a 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -112,7 +112,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). ## 6. Sequencing — seam first, silicon last -> **PR sequencing note.** This charter doc and its inbound ROADMAP link are one unit (the live doc-graph wall, `doc_reachability_project.rs`, fails on an orphan doc). The linking roadmap node (`accel-*`, incl. `accel-exec`) is authored in the roadmap-authority reconciliation **#5968** (single authority for the generated roadmap — kept out of this PR to avoid a generated-artifact merge collision). So this doc PR merges **after #5968 lands**; at that point the inbound link and the tracking rows are on main and the doc is reachable. Until then this PR is held (draft). +> **PR sequencing note.** This charter doc and its inbound ROADMAP link are one unit (the live doc-graph wall, `doc_reachability_project.rs`, fails on an orphan doc). The linking roadmap node (`accel-*`, incl. `accel-exec`) is authored in **loyal-bee-794's roadmap-authority content slice** — a decision-independent early follow-on to the #5968 *mechanism* PR (single authority for the generated roadmap — kept out of this PR to avoid a generated-artifact merge collision). So this doc PR merges **after that content slice lands on main**; at that point the inbound link and the tracking rows are present and the doc is reachable. Until then this PR is held (draft). 1. **Modeling lane** — `+LocalAccelerator` placement variant; the recognizer's output as a `RealizationPlan`; the `NumericalContract` type + its `DecodeFidelity` coupling; the refusal diagnostic. All in `std/` + `extdeps/languages//`. Lands consumed-or-marked (Ergonomics-lane "wire the seams" rule). 2. **Execution lane** — the recognizer pass (elementwise-array-fold detection over the core graph) + the SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter; the differential harness; the **integer bit-exact witness** + the **refusal witness**, green-by-execution with a red-on-revert discriminator. @@ -124,7 +124,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). - **Real today** (current v2 Rust interpreter, pre-self-host): the recognizer, the SoA fused-kernel handler, the differential + numerical-contract harness, the refusal arm, integer-bit-exact + float-under-contract bars. A runnable prototype, honestly labeled. - **Aspirational / post-self-host**: the plan being *fully* substrate-native end-to-end, and reshaping *arbitrary* programs (vs the recognized elementwise class). For the demo the plan is a real modeled value even where some lowering is Rust-side; each prototype-Rust seam is marked so the pitch never overclaims. -**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored in the roadmap reconciliation (#5968), and this charter is sequenced to merge **after** that row exists on main (which also provides this doc's inbound ROADMAP link — see the note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: +**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored in loyal-bee-794's roadmap-authority content slice (the follow-on to the #5968 mechanism PR), and this charter is sequenced to merge **after** that row exists on main (which also provides this doc's inbound ROADMAP link — see the note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: - *recognizer* → dissolves into a `.dag` **lens** (read-only over the `Node` tree) once the lens can express the elementwise-fold predicate; dissolution trigger `feature:dag-elementwise-recognizer-lens`. - *SoA fused-kernel handler* → dissolves into a `.dag` **Realization handler** bound to the `extdeps/languages/` target row (emit is the same fold, both directions); trigger `feature:dag-kernel-realization-handler`. From 2d9d6bc3cd797aacbf09022d19510472d6fa0e5e Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Mon, 29 Jun 2026 23:29:20 +0000 Subject: [PATCH 13/14] =?UTF-8?q?charter:=20atomic-ready=20=E2=80=94=20dro?= =?UTF-8?q?p=20#5969-specific=20sequencing=20scaffolding=20(doc=20folds=20?= =?UTF-8?q?into=20roadmap=20content=20slice)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit loyal-bee-794 takes option 2: cherry-picks this doc + authors the inbound link (accel-model plan_ptr) in the same commit of her roadmap content slice. Replace the 'this PR merges after / held draft' note with an atomic authoring note so the lifted version is correct. #5969 closes as superseded. Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index baffb69105a..c23b0b063f6 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -112,7 +112,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). ## 6. Sequencing — seam first, silicon last -> **PR sequencing note.** This charter doc and its inbound ROADMAP link are one unit (the live doc-graph wall, `doc_reachability_project.rs`, fails on an orphan doc). The linking roadmap node (`accel-*`, incl. `accel-exec`) is authored in **loyal-bee-794's roadmap-authority content slice** — a decision-independent early follow-on to the #5968 *mechanism* PR (single authority for the generated roadmap — kept out of this PR to avoid a generated-artifact merge collision). So this doc PR merges **after that content slice lands on main**; at that point the inbound link and the tracking rows are present and the doc is reachable. Until then this PR is held (draft). +> **Authoring note.** This charter doc and its inbound ROADMAP link land **atomically** (the live doc-graph wall, `doc_reachability_project.rs`, fails on an orphan doc). The linking roadmap node (`accel-*`, incl. `accel-exec`) is authored in **loyal-bee-794's roadmap-authority content slice** — the single authority for the generated roadmap — and the `accel-model` node carries the `plan_ptr` to this doc in the same commit, so the doc-graph wall is satisfied without a separate PR. 1. **Modeling lane** — `+LocalAccelerator` placement variant; the recognizer's output as a `RealizationPlan`; the `NumericalContract` type + its `DecodeFidelity` coupling; the refusal diagnostic. All in `std/` + `extdeps/languages//`. Lands consumed-or-marked (Ergonomics-lane "wire the seams" rule). 2. **Execution lane** — the recognizer pass (elementwise-array-fold detection over the core graph) + the SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter; the differential harness; the **integer bit-exact witness** + the **refusal witness**, green-by-execution with a red-on-revert discriminator. @@ -124,7 +124,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). - **Real today** (current v2 Rust interpreter, pre-self-host): the recognizer, the SoA fused-kernel handler, the differential + numerical-contract harness, the refusal arm, integer-bit-exact + float-under-contract bars. A runnable prototype, honestly labeled. - **Aspirational / post-self-host**: the plan being *fully* substrate-native end-to-end, and reshaping *arbitrary* programs (vs the recognized elementwise class). For the demo the plan is a real modeled value even where some lowering is Rust-side; each prototype-Rust seam is marked so the pitch never overclaims. -**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored in loyal-bee-794's roadmap-authority content slice (the follow-on to the #5968 mechanism PR), and this charter is sequenced to merge **after** that row exists on main (which also provides this doc's inbound ROADMAP link — see the note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: +**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored alongside this doc in loyal-bee-794's roadmap-authority content slice (see the authoring note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: - *recognizer* → dissolves into a `.dag` **lens** (read-only over the `Node` tree) once the lens can express the elementwise-fold predicate; dissolution trigger `feature:dag-elementwise-recognizer-lens`. - *SoA fused-kernel handler* → dissolves into a `.dag` **Realization handler** bound to the `extdeps/languages/` target row (emit is the same fold, both directions); trigger `feature:dag-kernel-realization-handler`. From bd6376264dd7aacc7993cb73a7ccb2cb763fe3de Mon Sep 17 00:00:00 2001 From: Brian Searls Date: Tue, 30 Jun 2026 11:14:27 +0000 Subject: [PATCH 14/14] Merge main; expand charter to full version (intuition + relational projection + fidelity-home fix) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit #5970 landed a minimal (mid-stream) snapshot of the charter; this restores the full content: §0.5 intuition (arbitrary program DAG -> numerical graph, operator-requested), §1.5 relational-projection deliverable (operator-requested), the cursor F1/F2 fixes (DecodeFidelity homed in extdeps/communication/medium.dag; narrowed inert claim; self-contained scaffold receipt), and corrects the authoring note to reflect that the doc is reachable on main via the .dag bind: pointer (not a roadmap-slice dependency). Co-Authored-By: Claude Opus 4.8 (1M context) --- docs/plans/accelerator-demo-roundtrip.md | 25 ++---------------------- 1 file changed, 2 insertions(+), 23 deletions(-) diff --git a/docs/plans/accelerator-demo-roundtrip.md b/docs/plans/accelerator-demo-roundtrip.md index 7e2d522eda1..9aa85f5f853 100644 --- a/docs/plans/accelerator-demo-roundtrip.md +++ b/docs/plans/accelerator-demo-roundtrip.md @@ -13,7 +13,6 @@ This draft is downstream of [DESIGN.md](../../DESIGN.md) §4 (one grammar, both - **NOT opcode-bucketing scattered scalars.** SIMT width must come from *data-parallelism inside a node* (one op over a contiguous array), not *task-parallelism across nodes* (gathering scattered scalar ops by opcode — the gather/scatter is itself the pointer-chasing you were trying to escape, and the arithmetic intensity is hopeless). - **NOT a general "reshape arbitrary programs" control plane.** That is post-self-host research. This demo handles exactly one recognized class: **pure elementwise array folds.** -<<<<<<< HEAD ## 0.5. Intuition — how your programs relate to GPU execution (the shared language) The phrase to hold onto is **"arbitrary program DAG → numerical graph."** Your program is already a dependency graph; the accelerator wants a *particular kind* of dependency graph. The demo is the bridge that finds the second kind inside the first. @@ -41,8 +40,6 @@ A GPU is essentially a **batch executor for arithmetic**: if at one moment you c So the one-sentence relationship: **your arbitrary program is a task DAG; inside it live numerical subgraphs; the demo recognizes one, chooses a layout that makes it SIMT-shaped, and lowers it — proving the recognition is semantics-exact or honestly refused.** -======= ->>>>>>> origin/main ## 1. The claim the demo proves (load-bearing) > A pure `.dag` elementwise-array subgraph can be lowered to a contiguous-layout, fused, data-parallel kernel; the result is **bit-identical to the scalar interpreter under a declared numerical contract**; and any subgraph outside the lowerable class is **refused** with a typed, located honesty diagnostic — never silently miscompiled. @@ -53,7 +50,6 @@ Three things an XLA/NVIDIA audience treats as *hard* and this gets *structurally 2. **A new backend is a *row*, not a backend team.** Medium-agnostic emit (§4/§7) means "support this accelerator" = author a target row in `extdeps/languages//`, not fork a codegen. The optional GPU run is the proof: *same plan, one target row changed.* 3. **The schedule/layout is data, so auto-tuning can't miscompile.** The plan is a first-class `RealizationPlan` value and every rewrite is provably semantics-preserving (purity + explicit `EffectShape`), so searching over layouts is guaranteed meaning-preserving. -<<<<<<< HEAD ## 1.5. The relational projection — the demo artifact that is *for the author* (and doubles as the pitch) A first-class deliverable, not a debug print: the demo must **render the relationship** "arbitrary program DAG → numerical graph → kernel" as an inspectable artifact, because making that relationship legible is half the point (to the author, who thinks in array compilers; and to the audience, who thinks in HLO). The **recognize + plan** station's `RealizationPlan` value is *promoted from a side-effect to the product.* @@ -78,13 +74,6 @@ The substrate **already models** the vocabulary; the roadmap (Ergonomics LANE) f - `std/realization.dag`: `Placement = LocalInProcess | LocalFilesystem | RemoteNetwork`, `Materialization = Recompute | Memoize | Share`, `RealizedStep { shape, placement, materialization }`, `RealizationPlan`, `RealizationObjective`. - `extdeps/communication/medium.dag`: `DecodeFidelity = Lossless | Lossy` (the honesty-boundary type — declared here, an extdeps-layer type, *not* in std; consume it, never re-fork it). -======= -## 2. On-model framing — first live consumer of the inert placement carriers - -The substrate **already models** the vocabulary; the roadmap (Ergonomics LANE) flags `Placement` / `Materialization` / `RealizationObjective` as *inert (no live consumer)* — the keystone inert-abstraction-lens's first RED witness. This demo makes them **load-bearing** by being their first real consumer: - -- `std/realization.dag`: `Placement = LocalInProcess | LocalFilesystem | RemoteNetwork`, `Materialization = Recompute | Memoize | Share`, `RealizedStep { shape, placement, materialization }`, `DecodeFidelity`, `RealizationPlan`, `RealizationObjective`. ->>>>>>> origin/main - `std/realization_schedule.dag`: `RealizationPlan`, `Runnable`, `Schedule = List>`, cost accounting. - `product/placement_supply.dag`: `PlacementSupplyRow` (host capacity) — literally "shaping for **supply**." @@ -106,11 +95,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). | 2. recognize + plan ("shaping for supply") | the elementwise-array-fold subgraph → a `RealizationPlan` value: contiguous SoA buffers, 3 ops fused into one pass, `placement: LocalAccelerator`. **Inspectable, printed.** | `std/realization.dag`, `std/realization_schedule.dag` (first live consumer) | | 3. lower → fused kernel (forward fold) | the *same* translate fold run backward → one fused contiguous-loop / SIMD kernel | `target_model` translate + new `extdeps/languages/` row | | 4. differential vs oracle | scalar interpreter on same input = ground truth; assert match on a discriminating input | existing v2 interpreter | -<<<<<<< HEAD | 5. fail-closed arm | feed a non-elementwise / effectful subgraph (data-dependent gather, or carries an effect) → **typed located `DecodeFidelity` refusal**, no silent fallback | `extdeps/communication/medium.dag` `DecodeFidelity` | -======= -| 5. fail-closed arm | feed a non-elementwise / effectful subgraph (data-dependent gather, or carries an effect) → **typed located `DecodeFidelity` refusal**, no silent fallback | `std/realization.dag` `DecodeFidelity` | ->>>>>>> origin/main ## 4. Acceptance bars (this is what makes it credible to *that* audience) @@ -127,11 +112,8 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). ## 6. Sequencing — seam first, silicon last -<<<<<<< HEAD -> **Authoring note.** This charter doc and its inbound ROADMAP link land **atomically** (the live doc-graph wall, `doc_reachability_project.rs`, fails on an orphan doc). The linking roadmap node (`accel-*`, incl. `accel-exec`) is authored in **loyal-bee-794's roadmap-authority content slice** — the single authority for the generated roadmap — and the `accel-model` node carries the `plan_ptr` to this doc in the same commit, so the doc-graph wall is satisfied without a separate PR. +> **Authoring note.** This doc landed on main with the modeling lane (#5970) and is kept reachable by the live doc-graph wall (`doc_reachability_project.rs`, which scans `bind:` provenance edges as well as markdown links) via the `bind: docs/plans/accelerator-demo-roundtrip.md` pointer in `dsl/gunbc/accelerator_demo_plan.dag` — so it is not an orphan. The optional ROADMAP *tracking* node (`accel-*`) lives in the roadmap-authority reconciliation (loyal-bee-794), separate from reachability. -======= ->>>>>>> origin/main 1. **Modeling lane** — `+LocalAccelerator` placement variant; the recognizer's output as a `RealizationPlan`; the `NumericalContract` type + its `DecodeFidelity` coupling; the refusal diagnostic. All in `std/` + `extdeps/languages//`. Lands consumed-or-marked (Ergonomics-lane "wire the seams" rule). 2. **Execution lane** — the recognizer pass (elementwise-array-fold detection over the core graph) + the SoA fused-kernel handler (CPU contiguous loop) in the v2 interpreter; the differential harness; the **integer bit-exact witness** + the **refusal witness**, green-by-execution with a red-on-revert discriminator. 3. **Numerical-contract bar** — float fixture under declared contract; refuse-on-contraction-violation witness. @@ -142,8 +124,7 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). - **Real today** (current v2 Rust interpreter, pre-self-host): the recognizer, the SoA fused-kernel handler, the differential + numerical-contract harness, the refusal arm, integer-bit-exact + float-under-contract bars. A runnable prototype, honestly labeled. - **Aspirational / post-self-host**: the plan being *fully* substrate-native end-to-end, and reshaping *arbitrary* programs (vs the recognized elementwise class). For the demo the plan is a real modeled value even where some lowering is Rust-side; each prototype-Rust seam is marked so the pitch never overclaims. -<<<<<<< HEAD -**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored alongside this doc in loyal-bee-794's roadmap-authority content slice (see the authoring note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: +**Hand-Rust scaffold receipt (§7 self-host — Rust shrinks to zero, so new Rust must name its exit).** The execution lane's three Rust additions on the v2-interpreter seed — the elementwise recognizer pass, the SoA fused-kernel handler, and the differential harness — are **explicitly scaffold, not load-bearing Rust.** The authority for each exit is the **named dissolution trigger declared right here** (self-contained in this charter); the roadmap *tracking* row for the lane is `accel-exec`, authored in loyal-bee-794's roadmap-authority reconciliation (separate from this doc's reachability — see the authoring note at the top of §6). The row does not flip `[x]` until each dissolution below is either done or re-deferred with a reason: - *recognizer* → dissolves into a `.dag` **lens** (read-only over the `Node` tree) once the lens can express the elementwise-fold predicate; dissolution trigger `feature:dag-elementwise-recognizer-lens`. - *SoA fused-kernel handler* → dissolves into a `.dag` **Realization handler** bound to the `extdeps/languages/` target row (emit is the same fold, both directions); trigger `feature:dag-kernel-realization-handler`. @@ -151,8 +132,6 @@ Fixture: a pure elementwise chain — `y = relu(a*b + c)` (mul → add → max). Until then they are `🟡`-marked prototype Rust on the doomed seed — they add **no** census ratchet pressure and must not be cemented into emit templates (DESIGN §7; the anti-cement rule). Net Rust delta is bounded and has a written path to zero; it is not new permanent compiler surface. -======= ->>>>>>> origin/main ## Open threads - Exact spelling of the accelerator `Placement` variant (device-parameterized `LocalAccelerator` vs flat) — DFS the concept DAG before minting; a device is plausibly a `Vendor`-adjacent entity (DESIGN §3), not a fresh enum.