diff --git a/dag/extdeps/ampere/nvparam.dag b/dag/extdeps/ampere/nvparam.dag new file mode 100644 index 00000000000..80a2ed07f67 --- /dev/null +++ b/dag/extdeps/ampere/nvparam.dag @@ -0,0 +1,614 @@ +module extdeps.ampere.nvparam + +import v2.std.algebra { filter } +import v2.std.collection { empty_map, map_insert, map_lookup } +import std.types { Int, List, Map, NonEmptyStr, String } +import std.measure { ByteSize, byte_size } +import std.decl_ref { DeclarationRef, WholeDeclaration } +import v2.std.optional { Present } +import extdeps.external_authority { ExternalAuthority, ExternalModelScope, ExternalSubjectRef } +import extdeps.uri { Uri, Https } + +// THE SUBJECT IS THE AMPERE ALTRA NON-VOLATILE PARAMETER (NVPARAM) KEY SPACE, as Ampere publishes it +// in edk2-platforms Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h (BSD-2-Clause-Patent) at the +// pinned commit. Every key below is transcribed mechanically from that header's +// `#define NV_SI_ (( * 8) + _START)` lines, under the header's own names: a key is +// the parameter's byte offset, 8 bytes per parameter, inside one of four regions whose bases the +// header declares (NV_PREBOOT_PARAM_START 0x0000, NV_MANU_PARAM_START 0x4000, NV_USER_PARAM_START +// 0x8000, NV_BOARD_PARAM_START 0xC000). +// +// THE HEADER ALSO STATES THE SPI-NOR LAYOUT: a Master copy the user may change and a "Last Known +// Copy" that "is handled by the fail safe" -- "a last know bootable copy" -- each holding a 16KB +// pre-boot region and a 32KB manufacturing-and-user region; and that the pre-boot parameters "will +// reset to default value on failsafe". NV_SI_FAILSAFE_RETRY (key 0x10) is one of them. What value a +// key holds, and what a value means, is NOT stated by the header and is not modeled here. + +data extdeps_external_authority_anchor: ExternalAuthority = ExternalAuthority { + uri: Uri { + scheme: Https + locator: "github.com/tianocore/edk2-platforms/blob/2170c80c622ed5353ac09e3335aafbbab8e40e4d/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h" + } +} + +data extdeps_model_scope: ExternalModelScope = ExternalModelScope { + subject: ExternalSubjectRef { + declaration: DeclarationRef { + module_path: "extdeps.ampere.nvparam", + decl_name: "NvParamKey", + field: WholeDeclaration + } + }, + first_citation: extdeps_external_authority_anchor, + further_citations: [] +} + +// The four regions, named by the header's *_PARAM_START defines. +type NvParamRegion + = NvPreboot + | NvManufacturing + | NvUser + | NvBoard + +type NvParamKey { + key: Int + name: NonEmptyStr + region: NvParamRegion +} + +// NVPARAM_SIZE (Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h `#define NVPARAM_SIZE 0x8`): +// the stride between keys, under the header's own name. +data nvparam_size: ByteSize = byte_size(count: 8) + +// Each region's first and last key, as the header defines them: NV_PREBOOT_PARAM_START 0x0000 and +// NV_PREBOOT_PARAM_MAX (86 * 8) + start; NV_MANU_PARAM_START 0x4000 and NV_MANU_PARAM_MAX (66 * 8) + +// start; NV_USER_PARAM_START 0x8000 and NV_USER_PARAM_MAX = NV_SI_PCIE_S1_RC7_AER_CE_INTERVAL; +// NV_BOARD_PARAM_START 0xC000 and NV_BOARD_PARAM_MAX (255 * 8) + start. PrintNVRAM walks each region +// from START to MAX inclusive in NVPARAM_SIZE steps, so these bound every key a dump can print. +fn nvparam_region_start(r: NvParamRegion) -> Int { + match r { NvPreboot => 0 NvManufacturing => 16384 NvUser => 32768 NvBoard => 49152 } +} + +fn nvparam_region_max(r: NvParamRegion) -> Int { + match r { NvPreboot => 688 NvManufacturing => 16912 NvUser => 33584 NvBoard => 51192 } +} + +data nvparam_keys: List = [ + NvParamKey { key: 8, name: "NV_SI_PCP_VDMC", region: NvPreboot }, + NvParamKey { key: 16, name: "NV_SI_FAILSAFE_RETRY", region: NvPreboot }, + NvParamKey { key: 24, name: "NV_SI_DDR_PPR_EN", region: NvPreboot }, + NvParamKey { key: 32, name: "NV_SI_DDR_RESERVED0", region: NvPreboot }, + NvParamKey { key: 40, name: "NV_SI_DDR_RESERVED1", region: NvPreboot }, + NvParamKey { key: 48, name: "NV_SI_DDR_LOG_LEVEL", region: NvPreboot }, + NvParamKey { key: 56, name: "NV_SI_DDR_RESERVED2", region: NvPreboot }, + NvParamKey { key: 64, name: "NV_SI_DDR_RD_DBI_EN", region: NvPreboot }, + NvParamKey { key: 72, name: "NV_SI_DDR_WR_DBI_EN", region: NvPreboot }, + NvParamKey { key: 80, name: "NV_SI_DDR_RETRY_EN", region: NvPreboot }, + NvParamKey { key: 88, name: "NV_SI_DDR_BANK_HASH_EN", region: NvPreboot }, + NvParamKey { key: 96, name: "NV_SI_DDR_RESERVED3", region: NvPreboot }, + NvParamKey { key: 104, name: "NV_SI_DDR_RCD_PARITY_EN", region: NvPreboot }, + NvParamKey { key: 112, name: "NV_SI_DDR_WRPATH_CLK_GATE_EN", region: NvPreboot }, + NvParamKey { key: 120, name: "NV_SI_DDR_IOCAL_MARGIN", region: NvPreboot }, + NvParamKey { key: 128, name: "NV_SI_DDR_RTR_S_MARGIN", region: NvPreboot }, + NvParamKey { key: 136, name: "NV_SI_DDR_RTR_L_MARGIN", region: NvPreboot }, + NvParamKey { key: 144, name: "NV_SI_DDR_RTR_CS_MARGIN", region: NvPreboot }, + NvParamKey { key: 152, name: "NV_SI_DDR_WTW_S_MARGIN", region: NvPreboot }, + NvParamKey { key: 160, name: "NV_SI_DDR_WTW_L_MARGIN", region: NvPreboot }, + NvParamKey { key: 168, name: "NV_SI_DDR_WTW_CS_MARGIN", region: NvPreboot }, + NvParamKey { key: 176, name: "NV_SI_DDR_RTW_S_MARGIN", region: NvPreboot }, + NvParamKey { key: 184, name: "NV_SI_DDR_RTW_L_MARGIN", region: NvPreboot }, + NvParamKey { key: 192, name: "NV_SI_DDR_RTW_CS_MARGIN", region: NvPreboot }, + NvParamKey { key: 200, name: "NV_SI_DDR_WTR_S_MARGIN", region: NvPreboot }, + NvParamKey { key: 208, name: "NV_SI_DDR_WTR_L_MARGIN", region: NvPreboot }, + NvParamKey { key: 216, name: "NV_SI_DDR_WTR_CS_MARGIN", region: NvPreboot }, + NvParamKey { key: 224, name: "NV_SI_DDR_PARITY_EN", region: NvPreboot }, + NvParamKey { key: 232, name: "NV_SI_SLC_DISABLE", region: NvPreboot }, + NvParamKey { key: 240, name: "NV_SI_SLC_SIZE", region: NvPreboot }, + NvParamKey { key: 248, name: "NV_SI_SLC_SCRUB", region: NvPreboot }, + NvParamKey { key: 256, name: "NV_SI_CCIX_DISABLE", region: NvPreboot }, + NvParamKey { key: 264, name: "NV_SI_ESM_RESERVED", region: NvPreboot }, + NvParamKey { key: 272, name: "NV_SI_DDR_PHY_CAL_MODE", region: NvPreboot }, + NvParamKey { key: 280, name: "NV_SI_RAS_TEST_EN", region: NvPreboot }, + NvParamKey { key: 288, name: "NV_SI_DDR_EYE_SCREEN_TEST_EN", region: NvPreboot }, + NvParamKey { key: 296, name: "NV_SI_DDR_EYE_MASK_RD_MARGIN", region: NvPreboot }, + NvParamKey { key: 304, name: "NV_SI_DDR_EYE_MASK_WR_MARGIN", region: NvPreboot }, + NvParamKey { key: 312, name: "NV_SI_DDR_RDODT_ON_MARGIN", region: NvPreboot }, + NvParamKey { key: 320, name: "NV_SI_DDR_RDODT_OFF_MARGIN", region: NvPreboot }, + NvParamKey { key: 328, name: "NV_SI_DDR_WRODT_ON_MARGIN", region: NvPreboot }, + NvParamKey { key: 336, name: "NV_SI_DDR_WRODT_OFF_MARGIN", region: NvPreboot }, + NvParamKey { key: 344, name: "NV_SI_SLC_OCM_EN", region: NvPreboot }, + NvParamKey { key: 352, name: "NV_SI_ESM_WIDTH", region: NvPreboot }, + NvParamKey { key: 360, name: "NV_SI_TM2_DISABLE", region: NvPreboot }, + NvParamKey { key: 368, name: "NV_SI_CPUPLL_FREQ_MHZ", region: NvPreboot }, + NvParamKey { key: 376, name: "NV_SI_DDR_ERR_INJECT_MASK_SK0", region: NvPreboot }, + NvParamKey { key: 384, name: "NV_SI_DDR_ERR_INJECT_MASK_SK1", region: NvPreboot }, + NvParamKey { key: 392, name: "NV_SI_CXG_DISABLE_EARLY_COMPACK", region: NvPreboot }, + NvParamKey { key: 400, name: "NV_SI_CXG_ENABLE_SAME_ADDR_COMP_ORDER", region: NvPreboot }, + NvParamKey { key: 408, name: "NV_SI_DDR_TURNAROUND_CONTROL", region: NvPreboot }, + NvParamKey { key: 416, name: "NV_SI_DDR_HIT_TURNAROUND_CONTROL", region: NvPreboot }, + NvParamKey { key: 424, name: "NV_SI_DDR_QOS_CLASS_CONTROL", region: NvPreboot }, + NvParamKey { key: 432, name: "NV_SI_DDR_ESCALATION_CONTROL", region: NvPreboot }, + NvParamKey { key: 440, name: "NV_SI_DDR_QV_CONTROL_31_00", region: NvPreboot }, + NvParamKey { key: 448, name: "NV_SI_DDR_QV_CONTROL_63_32", region: NvPreboot }, + NvParamKey { key: 456, name: "NV_SI_DDR_CREDIT_CONTROL", region: NvPreboot }, + NvParamKey { key: 464, name: "NV_SI_DDR_WRITE_PRIORITY_CONTROL_31_00", region: NvPreboot }, + NvParamKey { key: 472, name: "NV_SI_DDR_WRITE_PRIORITY_CONTROL_63_32", region: NvPreboot }, + NvParamKey { key: 480, name: "NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_31_00", region: NvPreboot }, + NvParamKey { key: 488, name: "NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_63_32", region: NvPreboot }, + NvParamKey { key: 496, name: "NV_SI_TFA_FAILURE_FAILSAFE", region: NvPreboot }, + NvParamKey { key: 504, name: "NV_SI_UEFI_FAILURE_FAILSAFE", region: NvPreboot }, + NvParamKey { key: 512, name: "NV_SI_DDR_STRIPE_DECODE", region: NvPreboot }, + NvParamKey { key: 520, name: "NV_SI_DDR_DEBUG_CTRL", region: NvPreboot }, + NvParamKey { key: 528, name: "NV_SI_CXG_RA_DEVNR_ORD_WFC_DIS", region: NvPreboot }, + NvParamKey { key: 536, name: "NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD", region: NvPreboot }, + NvParamKey { key: 544, name: "NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD_AC", region: NvPreboot }, + NvParamKey { key: 552, name: "NV_SI_DDR_PHY_INIT_UPDATE_CONFIG", region: NvPreboot }, + NvParamKey { key: 560, name: "NV_SI_DDR_PHY_UPDATE_CONTROL", region: NvPreboot }, + NvParamKey { key: 568, name: "NV_SI_PROFILE_EN", region: NvPreboot }, + NvParamKey { key: 576, name: "NV_SI_PCIE_PHY_SETTING", region: NvPreboot }, + NvParamKey { key: 584, name: "NV_SI_DDR_PHY_CAL_THRESHOLD", region: NvPreboot }, + NvParamKey { key: 592, name: "NV_SI_DDR_PHY_CAL_INTERVAL_CNT", region: NvPreboot }, + NvParamKey { key: 600, name: "NV_SI_RESERVED", region: NvPreboot }, + NvParamKey { key: 608, name: "NV_SI_S0_RHS_RCA_EN", region: NvPreboot }, + NvParamKey { key: 616, name: "NV_SI_S1_RHS_RCA_EN", region: NvPreboot }, + NvParamKey { key: 624, name: "NV_SI_2P_DPLL", region: NvPreboot }, + NvParamKey { key: 632, name: "NV_SI_2P_ALI_CFG", region: NvPreboot }, + NvParamKey { key: 640, name: "NV_SI_2P_ALI_CFG_LINK_RETRAIN", region: NvPreboot }, + NvParamKey { key: 648, name: "NV_SI_2P_ALI_CFG_CRC", region: NvPreboot }, + NvParamKey { key: 656, name: "NV_SI_DDR_RT_CONTROL_31_00", region: NvPreboot }, + NvParamKey { key: 664, name: "NV_SI_DDR_RT_CONTROL_63_32", region: NvPreboot }, + NvParamKey { key: 672, name: "NV_SI_DDR_TIMEOUT_CONTROL", region: NvPreboot }, + NvParamKey { key: 680, name: "NV_SI_CPU_LPI_FREQ_DISABLE", region: NvPreboot }, + NvParamKey { key: 688, name: "NV_SI_CPU_LPI_FREQ_ENERGY_THRSHLD", region: NvPreboot }, + NvParamKey { key: 16384, name: "NV_SI_DDR_VMARGIN", region: NvManufacturing }, + NvParamKey { key: 16392, name: "NV_SI_SOC_VMARGIN", region: NvManufacturing }, + NvParamKey { key: 16400, name: "NV_SI_AVS_VMARGIN", region: NvManufacturing }, + NvParamKey { key: 16408, name: "NV_SI_TPC_TM1_MARGIN", region: NvManufacturing }, + NvParamKey { key: 16416, name: "NV_SI_TPC_TM2_MARGIN", region: NvManufacturing }, + NvParamKey { key: 16424, name: "NV_SI_TPC_FREQ_THROTTLE", region: NvManufacturing }, + NvParamKey { key: 16432, name: "NV_SI_T_LTLM_EN", region: NvManufacturing }, + NvParamKey { key: 16440, name: "NV_SI_T_LTLM_THRSHLD", region: NvManufacturing }, + NvParamKey { key: 16448, name: "NV_SI_T_GTLM_THRSHLD", region: NvManufacturing }, + NvParamKey { key: 16456, name: "NV_SI_P_LM_EN", region: NvManufacturing }, + NvParamKey { key: 16464, name: "NV_SI_P_LM_THRSHLD", region: NvManufacturing }, + NvParamKey { key: 16472, name: "NV_SI_TPC_OVERTEMP_ISR_DISABLE", region: NvManufacturing }, + NvParamKey { key: 16480, name: "NV_SI_VPP_VMARGIN", region: NvManufacturing }, + NvParamKey { key: 16488, name: "NV_SI_PMPRO_FAILURE_FAILSAFE", region: NvManufacturing }, + NvParamKey { key: 16496, name: "NV_SI_FAILSAFE_DISABLE", region: NvManufacturing }, + NvParamKey { key: 16504, name: "NV_SI_PLIMIT_APM_DS_PERCENTAGE", region: NvManufacturing }, + NvParamKey { key: 16512, name: "NV_SI_PLIMIT_APM_EP_MS", region: NvManufacturing }, + NvParamKey { key: 16520, name: "NV_SI_PLIMIT_APM_PM1_PERCENTAGE_TDP", region: NvManufacturing }, + NvParamKey { key: 16528, name: "NV_SI_CPU_LPI_RESERVED0", region: NvManufacturing }, + NvParamKey { key: 16536, name: "NV_SI_CPU_LPI_RESERVED1", region: NvManufacturing }, + NvParamKey { key: 16544, name: "NV_SI_CCIX_OPT_CONFIG", region: NvManufacturing }, + NvParamKey { key: 16552, name: "NV_SI_MESH_FREQ_MARGIN", region: NvManufacturing }, + NvParamKey { key: 16560, name: "NV_SI_MESH_TURBO_EN", region: NvManufacturing }, + NvParamKey { key: 16568, name: "NV_SI_PWR_HEADROOM_WATT", region: NvManufacturing }, + NvParamKey { key: 16576, name: "NV_SI_EXTRA_PCP_VOLT_MV", region: NvManufacturing }, + NvParamKey { key: 16584, name: "NV_SI_CPU_LPI_HYST_CNT", region: NvManufacturing }, + NvParamKey { key: 16592, name: "NV_SI_DVFS_VOLT_INC_STEP_MV", region: NvManufacturing }, + NvParamKey { key: 16600, name: "NV_SI_DVFS_VOLT_DEC_STEP_MV", region: NvManufacturing }, + NvParamKey { key: 16608, name: "NV_SI_PLIMIT_APM_TEMP_THLD", region: NvManufacturing }, + NvParamKey { key: 16616, name: "NV_SI_PLIMIT_APM_EN", region: NvManufacturing }, + NvParamKey { key: 16624, name: "NV_SI_VDM_EN", region: NvManufacturing }, + NvParamKey { key: 16632, name: "NV_SI_VDM_VMARGIN_MV", region: NvManufacturing }, + NvParamKey { key: 16640, name: "NV_SI_PLT_EN", region: NvManufacturing }, + NvParamKey { key: 16648, name: "NV_SI_PLT_SOCKET", region: NvManufacturing }, + NvParamKey { key: 16656, name: "NV_SI_PLT_MCU_MASK", region: NvManufacturing }, + NvParamKey { key: 16664, name: "NV_SI_PLT_RANK_MASK", region: NvManufacturing }, + NvParamKey { key: 16672, name: "NV_SI_PLT_SLICE_MASK", region: NvManufacturing }, + NvParamKey { key: 16680, name: "NV_SI_PLT_BIT_MASK", region: NvManufacturing }, + NvParamKey { key: 16688, name: "NV_SI_PLT_X_PARAM", region: NvManufacturing }, + NvParamKey { key: 16696, name: "NV_SI_PLT_Y_PARAM", region: NvManufacturing }, + NvParamKey { key: 16704, name: "NV_SI_PLT_X_LEFT", region: NvManufacturing }, + NvParamKey { key: 16712, name: "NV_SI_PLT_X_RIGHT", region: NvManufacturing }, + NvParamKey { key: 16720, name: "NV_SI_PLT_X_STEP", region: NvManufacturing }, + NvParamKey { key: 16728, name: "NV_SI_PLT_Y_BOTTOM", region: NvManufacturing }, + NvParamKey { key: 16736, name: "NV_SI_PLT_Y_TOP", region: NvManufacturing }, + NvParamKey { key: 16744, name: "NV_SI_PLT_Y_STEP", region: NvManufacturing }, + NvParamKey { key: 16752, name: "NV_SI_PLT_START_ADDR_LO", region: NvManufacturing }, + NvParamKey { key: 16760, name: "NV_SI_PLT_START_ADDR_UP", region: NvManufacturing }, + NvParamKey { key: 16768, name: "NV_SI_PLT_SIZE", region: NvManufacturing }, + NvParamKey { key: 16776, name: "NV_SI_PLT_THREAD_CNT", region: NvManufacturing }, + NvParamKey { key: 16784, name: "NV_SI_PLT_SCREEN", region: NvManufacturing }, + NvParamKey { key: 16792, name: "NV_SI_PLT_RSVD", region: NvManufacturing }, + NvParamKey { key: 16800, name: "NV_SI_DVFS_VOLT_CHANGE_BY_STEP_EN", region: NvManufacturing }, + NvParamKey { key: 16824, name: "NV_SI_CCIX_DIAG_CTRL1", region: NvManufacturing }, + NvParamKey { key: 16832, name: "NV_SI_CCIX_DIAG_CTRL2", region: NvManufacturing }, + NvParamKey { key: 16840, name: "NV_SI_DDR_TCAL_EN", region: NvManufacturing }, + NvParamKey { key: 16848, name: "NV_SI_DDR_TCAL_DIMM_LOW_TEMP_THRESHOLD", region: NvManufacturing }, + NvParamKey { key: 16856, name: "NV_SI_DDR_TCAL_DIMM_HIGH_TEMP_THRESHOLD", region: NvManufacturing }, + NvParamKey { key: 16864, name: "NV_SI_DDR_TCAL_MCU_LOW_TEMP_THRESHOLD", region: NvManufacturing }, + NvParamKey { key: 16872, name: "NV_SI_DDR_TCAL_MCU_HIGH_TEMP_THRESHOLD", region: NvManufacturing }, + NvParamKey { key: 16880, name: "NV_SI_DDR_TCAL_LOW_TEMP_VOLT_OFF_MV", region: NvManufacturing }, + NvParamKey { key: 16888, name: "NV_SI_DDR_TCAL_PERIOD_SEC", region: NvManufacturing }, + NvParamKey { key: 16896, name: "NV_SI_DDR_TCAL_SOC_VOLT_CAP_MV", region: NvManufacturing }, + NvParamKey { key: 16904, name: "NV_SI_ALTRAMAX_ICCMAX_EN", region: NvManufacturing }, + NvParamKey { key: 16912, name: "NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD", region: NvManufacturing }, + NvParamKey { key: 16920, name: "NV_SI_ALTRAMAX_ICCMAX_OC_LIMIT_MARGIN", region: NvManufacturing }, + NvParamKey { key: 16928, name: "NV_SI_SLT_VREF_EXT_PROG_EN", region: NvManufacturing }, + NvParamKey { key: 16936, name: "NV_SI_SLT_FLAGS", region: NvManufacturing }, + NvParamKey { key: 32768, name: "NV_SI_S0_PCP_ACTIVECPM_0_31", region: NvUser }, + NvParamKey { key: 32776, name: "NV_SI_S0_PCP_ACTIVECPM_32_63", region: NvUser }, + NvParamKey { key: 32784, name: "NV_SI_S1_PCP_ACTIVECPM_0_31", region: NvUser }, + NvParamKey { key: 32792, name: "NV_SI_S1_PCP_ACTIVECPM_32_63", region: NvUser }, + NvParamKey { key: 32800, name: "NV_SI_WDT_BIOS_EXP_MINS", region: NvUser }, + NvParamKey { key: 32808, name: "NV_SI_DDR_CE_RAS_THRESHOLD", region: NvUser }, + NvParamKey { key: 32816, name: "NV_SI_DDR_CE_RAS_INTERVAL", region: NvUser }, + NvParamKey { key: 32824, name: "NV_SI_DDR_SPEED", region: NvUser }, + NvParamKey { key: 32832, name: "NV_SI_DDR_SCRUB_EN", region: NvUser }, + NvParamKey { key: 32840, name: "NV_SI_DDR_ECC_MODE", region: NvUser }, + NvParamKey { key: 32848, name: "NV_SI_S0_RCA_PCI_DEVMAP", region: NvUser }, + NvParamKey { key: 32856, name: "NV_SI_S0_RCB_PCI_DEVMAP", region: NvUser }, + NvParamKey { key: 32864, name: "NV_SI_S1_RCA_PCI_DEVMAP", region: NvUser }, + NvParamKey { key: 32872, name: "NV_SI_S1_RCB_PCI_DEVMAP", region: NvUser }, + NvParamKey { key: 32880, name: "NV_SI_DDR_ERRCTRL", region: NvUser }, + NvParamKey { key: 32888, name: "NV_SI_DDR_REFRESH_GRANULARITY", region: NvUser }, + NvParamKey { key: 32896, name: "NV_SI_SUBNUMA_MODE", region: NvUser }, + NvParamKey { key: 32904, name: "NV_SI_ERRATUM_1542419_WA", region: NvUser }, + NvParamKey { key: 32912, name: "NV_SI_NEAR_ATOMIC_DISABLE", region: NvUser }, + NvParamKey { key: 32920, name: "NV_SI_DDR_SLAVE_32BIT_MEM_EN", region: NvUser }, + NvParamKey { key: 32928, name: "NV_SI_CPUECTLR_EL1_0_31", region: NvUser }, + NvParamKey { key: 32936, name: "NV_SI_CPUECTLR_EL1_32_63", region: NvUser }, + NvParamKey { key: 32944, name: "NV_SI_HARDWARE_EINJ", region: NvUser }, + NvParamKey { key: 32952, name: "NV_SI_2P_CE_RAS_THRESHOLD", region: NvUser }, + NvParamKey { key: 32960, name: "NV_SI_2P_CE_RAS_INTERVAL", region: NvUser }, + NvParamKey { key: 32968, name: "NV_SI_RAS_BERT_ENABLED", region: NvUser }, + NvParamKey { key: 32976, name: "NV_SI_HNF_AUX_CTL_0_31", region: NvUser }, + NvParamKey { key: 32984, name: "NV_SI_HNF_AUX_CTL_32_63", region: NvUser }, + NvParamKey { key: 32992, name: "NV_SI_CPM_CE_RAS_THRESHOLD", region: NvUser }, + NvParamKey { key: 33000, name: "NV_SI_CPM_CE_RAS_INTERVAL", region: NvUser }, + NvParamKey { key: 33008, name: "NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33016, name: "NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33024, name: "NV_SI_DDR_WR_BACK_EN", region: NvUser }, + NvParamKey { key: 33032, name: "NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33040, name: "NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33048, name: "NV_SI_LINK_ERR_THRESHOLD", region: NvUser }, + NvParamKey { key: 33056, name: "NV_SI_SEC_WDT_BIOS_EXP_MINS", region: NvUser }, + NvParamKey { key: 33064, name: "NV_SI_NVDIMM_MODE", region: NvUser }, + NvParamKey { key: 33072, name: "NV_SI_RAS_SDEI_ENABLED", region: NvUser }, + NvParamKey { key: 33080, name: "NV_SI_NVDIMM_PROV_MASK_S0", region: NvUser }, + NvParamKey { key: 33088, name: "NV_SI_NVDIMM_PROV_MASK_S1", region: NvUser }, + NvParamKey { key: 33096, name: "NV_SI_DDR_ZQCS_EN", region: NvUser }, + NvParamKey { key: 33104, name: "NV_SI_DDR_CRC_MODE", region: NvUser }, + NvParamKey { key: 33112, name: "NV_SI_CXG_RA_AUX_CTL_0_31", region: NvUser }, + NvParamKey { key: 33120, name: "NV_SI_CXG_RA_AUX_CTL_32_63", region: NvUser }, + NvParamKey { key: 33128, name: "NV_SI_CXG_RA_AUX_CTL_0_31_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33136, name: "NV_SI_CXG_RA_AUX_CTL_32_63_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33144, name: "NV_SI_CXLA_AUX_CTL_0_31", region: NvUser }, + NvParamKey { key: 33152, name: "NV_SI_CXLA_AUX_CTL_32_63", region: NvUser }, + NvParamKey { key: 33160, name: "NV_SI_CXLA_AUX_CTL_0_31_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33168, name: "NV_SI_CXLA_AUX_CTL_32_63_WR_EN_MASK", region: NvUser }, + NvParamKey { key: 33176, name: "NV_SI_DDR_LOW_POWER_CFG", region: NvUser }, + NvParamKey { key: 33184, name: "NV_SI_ALERT_DIMM_SHUTDOWN_EN", region: NvUser }, + NvParamKey { key: 33192, name: "NV_SI_DFS_EN", region: NvUser }, + NvParamKey { key: 33200, name: "NV_SI_RAS_PCIE_AER_FW_FIRST", region: NvUser }, + NvParamKey { key: 33208, name: "NV_SI_RAS_DRAM_EINJ_NOTRIGGER", region: NvUser }, + NvParamKey { key: 33216, name: "NV_SI_RAS_AEST_PROC_EN", region: NvUser }, + NvParamKey { key: 33224, name: "NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN", region: NvUser }, + NvParamKey { key: 33232, name: "NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN", region: NvUser }, + NvParamKey { key: 33240, name: "NV_SI_2P_RESERVED0", region: NvUser }, + NvParamKey { key: 33248, name: "NV_SI_2P_RESERVED1", region: NvUser }, + NvParamKey { key: 33256, name: "NV_SI_2P_RESERVED2", region: NvUser }, + NvParamKey { key: 33264, name: "NV_SI_HCR_EL2_CTL_LOW", region: NvUser }, + NvParamKey { key: 33272, name: "NV_SI_HCR_EL2_CTL_HIGH", region: NvUser }, + NvParamKey { key: 33280, name: "NV_SI_ESM_SPEED", region: NvUser }, + NvParamKey { key: 33288, name: "NV_SI_RAS_DDR_CE_TH1", region: NvUser }, + NvParamKey { key: 33296, name: "NV_SI_RAS_DDR_CE_TH2", region: NvUser }, + NvParamKey { key: 33304, name: "NV_SI_RAS_DDR_CE_WINDOW1", region: NvUser }, + NvParamKey { key: 33312, name: "NV_SI_RAS_DDR_CE_WINDOW2", region: NvUser }, + NvParamKey { key: 33320, name: "NV_SI_RAS_2P_CE_FILTER_THRESHOLD", region: NvUser }, + NvParamKey { key: 33328, name: "NV_SI_RAS_2P_CE_FILTER_WINDOW", region: NvUser }, + NvParamKey { key: 33336, name: "NV_SI_PCIE_S0_RC0_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33344, name: "NV_SI_PCIE_S0_RC0_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33352, name: "NV_SI_PCIE_S0_RC1_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33360, name: "NV_SI_PCIE_S0_RC1_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33368, name: "NV_SI_PCIE_S0_RC2_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33376, name: "NV_SI_PCIE_S0_RC2_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33384, name: "NV_SI_PCIE_S0_RC3_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33392, name: "NV_SI_PCIE_S0_RC3_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33400, name: "NV_SI_PCIE_S0_RC4_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33408, name: "NV_SI_PCIE_S0_RC4_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33416, name: "NV_SI_PCIE_S0_RC5_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33424, name: "NV_SI_PCIE_S0_RC5_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33432, name: "NV_SI_PCIE_S0_RC6_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33440, name: "NV_SI_PCIE_S0_RC6_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33448, name: "NV_SI_PCIE_S0_RC7_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33456, name: "NV_SI_PCIE_S0_RC7_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33464, name: "NV_SI_PCIE_S1_RC0_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33472, name: "NV_SI_PCIE_S1_RC0_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33480, name: "NV_SI_PCIE_S1_RC1_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33488, name: "NV_SI_PCIE_S1_RC1_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33496, name: "NV_SI_PCIE_S1_RC2_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33504, name: "NV_SI_PCIE_S1_RC2_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33512, name: "NV_SI_PCIE_S1_RC3_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33520, name: "NV_SI_PCIE_S1_RC3_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33528, name: "NV_SI_PCIE_S1_RC4_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33536, name: "NV_SI_PCIE_S1_RC4_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33544, name: "NV_SI_PCIE_S1_RC5_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33552, name: "NV_SI_PCIE_S1_RC5_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33560, name: "NV_SI_PCIE_S1_RC6_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33568, name: "NV_SI_PCIE_S1_RC6_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 33576, name: "NV_SI_PCIE_S1_RC7_AER_CE_THRESHOLD", region: NvUser }, + NvParamKey { key: 33584, name: "NV_SI_PCIE_S1_RC7_AER_CE_INTERVAL", region: NvUser }, + NvParamKey { key: 49152, name: "NV_SI_RO_BOARD_VENDOR", region: NvBoard }, + NvParamKey { key: 49160, name: "NV_SI_RO_BOARD_TYPE", region: NvBoard }, + NvParamKey { key: 49168, name: "NV_SI_RO_BOARD_REV", region: NvBoard }, + NvParamKey { key: 49176, name: "NV_SI_RO_BOARD_CFG", region: NvBoard }, + NvParamKey { key: 49184, name: "NV_SI_RO_BOARD_S0_DIMM_AVAIL", region: NvBoard }, + NvParamKey { key: 49192, name: "NV_SI_RO_BOARD_S1_DIMM_AVAIL", region: NvBoard }, + NvParamKey { key: 49200, name: "NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49208, name: "NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49216, name: "NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49224, name: "NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49232, name: "NV_SI_RO_BOARD_TPM_LOC", region: NvBoard }, + NvParamKey { key: 49240, name: "NV_SI_RO_BOARD_I2C0_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49248, name: "NV_SI_RO_BOARD_I2C1_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49256, name: "NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49264, name: "NV_SI_RO_BOARD_I2C3_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49272, name: "NV_SI_RO_BOARD_I2C9_FREQ_KHZ", region: NvBoard }, + NvParamKey { key: 49280, name: "NV_SI_RO_BOARD_2P_CFG", region: NvBoard }, + NvParamKey { key: 49288, name: "NV_SI_RO_BOARD_S0_RCA0_CFG", region: NvBoard }, + NvParamKey { key: 49296, name: "NV_SI_RO_BOARD_S0_RCA1_CFG", region: NvBoard }, + NvParamKey { key: 49304, name: "NV_SI_RO_BOARD_S0_RCA2_CFG", region: NvBoard }, + NvParamKey { key: 49312, name: "NV_SI_RO_BOARD_S0_RCA3_CFG", region: NvBoard }, + NvParamKey { key: 49320, name: "NV_SI_RO_BOARD_S0_RCB0_LO_CFG", region: NvBoard }, + NvParamKey { key: 49328, name: "NV_SI_RO_BOARD_S0_RCB0_HI_CFG", region: NvBoard }, + NvParamKey { key: 49336, name: "NV_SI_RO_BOARD_S0_RCB1_LO_CFG", region: NvBoard }, + NvParamKey { key: 49344, name: "NV_SI_RO_BOARD_S0_RCB1_HI_CFG", region: NvBoard }, + NvParamKey { key: 49352, name: "NV_SI_RO_BOARD_S0_RCB2_LO_CFG", region: NvBoard }, + NvParamKey { key: 49360, name: "NV_SI_RO_BOARD_S0_RCB2_HI_CFG", region: NvBoard }, + NvParamKey { key: 49368, name: "NV_SI_RO_BOARD_S0_RCB3_LO_CFG", region: NvBoard }, + NvParamKey { key: 49376, name: "NV_SI_RO_BOARD_S0_RCB3_HI_CFG", region: NvBoard }, + NvParamKey { key: 49384, name: "NV_SI_RO_BOARD_S1_RCA0_CFG", region: NvBoard }, + NvParamKey { key: 49392, name: "NV_SI_RO_BOARD_S1_RCA1_CFG", region: NvBoard }, + NvParamKey { key: 49400, name: "NV_SI_RO_BOARD_S1_RCA2_CFG", region: NvBoard }, + NvParamKey { key: 49408, name: "NV_SI_RO_BOARD_S1_RCA3_CFG", region: NvBoard }, + NvParamKey { key: 49416, name: "NV_SI_RO_BOARD_S1_RCB0_LO_CFG", region: NvBoard }, + NvParamKey { key: 49424, name: "NV_SI_RO_BOARD_S1_RCB0_HI_CFG", region: NvBoard }, + NvParamKey { key: 49432, name: "NV_SI_RO_BOARD_S1_RCB1_LO_CFG", region: NvBoard }, + NvParamKey { key: 49440, name: "NV_SI_RO_BOARD_S1_RCB1_HI_CFG", region: NvBoard }, + NvParamKey { key: 49448, name: "NV_SI_RO_BOARD_S1_RCB2_LO_CFG", region: NvBoard }, + NvParamKey { key: 49456, name: "NV_SI_RO_BOARD_S1_RCB2_HI_CFG", region: NvBoard }, + NvParamKey { key: 49464, name: "NV_SI_RO_BOARD_S1_RCB3_LO_CFG", region: NvBoard }, + NvParamKey { key: 49472, name: "NV_SI_RO_BOARD_S1_RCB3_HI_CFG", region: NvBoard }, + NvParamKey { key: 49480, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_P0", region: NvBoard }, + NvParamKey { key: 49488, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_P1", region: NvBoard }, + NvParamKey { key: 49496, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_P2", region: NvBoard }, + NvParamKey { key: 49504, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_P3", region: NvBoard }, + NvParamKey { key: 49512, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_M1", region: NvBoard }, + NvParamKey { key: 49520, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_M2", region: NvBoard }, + NvParamKey { key: 49528, name: "NV_SI_RO_BOARD_T_LTLM_DELTA_M3", region: NvBoard }, + NvParamKey { key: 49536, name: "NV_SI_RO_BOARD_P_LM_PID_P", region: NvBoard }, + NvParamKey { key: 49544, name: "NV_SI_RO_BOARD_P_LM_PID_I", region: NvBoard }, + NvParamKey { key: 49552, name: "NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD", region: NvBoard }, + NvParamKey { key: 49560, name: "NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD", region: NvBoard }, + NvParamKey { key: 49568, name: "NV_SI_RO_BOARD_P_LM_PID_D", region: NvBoard }, + NvParamKey { key: 49576, name: "NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST", region: NvBoard }, + NvParamKey { key: 49584, name: "NV_SI_RO_BOARD_TPM_ALG_ID", region: NvBoard }, + NvParamKey { key: 49592, name: "NV_SI_RO_BOARD_DDR_SPEED_GRADE", region: NvBoard }, + NvParamKey { key: 49600, name: "NV_SI_RO_BOARD_DDR_S0_RTT_WR", region: NvBoard }, + NvParamKey { key: 49608, name: "NV_SI_RO_BOARD_DDR_S1_RTT_WR", region: NvBoard }, + NvParamKey { key: 49616, name: "NV_SI_RO_BOARD_DDR_S0_RTT_NOM", region: NvBoard }, + NvParamKey { key: 49624, name: "NV_SI_RO_BOARD_DDR_S1_RTT_NOM", region: NvBoard }, + NvParamKey { key: 49632, name: "NV_SI_RO_BOARD_DDR_S0_RTT_PARK", region: NvBoard }, + NvParamKey { key: 49640, name: "NV_SI_RO_BOARD_DDR_S1_RTT_PARK", region: NvBoard }, + NvParamKey { key: 49648, name: "NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49656, name: "NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49664, name: "NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49672, name: "NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49680, name: "NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49688, name: "NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49696, name: "NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49704, name: "NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49712, name: "NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49720, name: "NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49728, name: "NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49736, name: "NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC", region: NvBoard }, + NvParamKey { key: 49744, name: "NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49752, name: "NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49760, name: "NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49768, name: "NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC", region: NvBoard }, + NvParamKey { key: 49776, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC", region: NvBoard }, + NvParamKey { key: 49784, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC", region: NvBoard }, + NvParamKey { key: 49792, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC", region: NvBoard }, + NvParamKey { key: 49800, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC", region: NvBoard }, + NvParamKey { key: 49808, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC", region: NvBoard }, + NvParamKey { key: 49816, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC", region: NvBoard }, + NvParamKey { key: 49824, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC", region: NvBoard }, + NvParamKey { key: 49832, name: "NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC", region: NvBoard }, + NvParamKey { key: 49840, name: "NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC", region: NvBoard }, + NvParamKey { key: 49848, name: "NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC", region: NvBoard }, + NvParamKey { key: 49856, name: "NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC", region: NvBoard }, + NvParamKey { key: 49864, name: "NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC", region: NvBoard }, + NvParamKey { key: 49872, name: "NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT", region: NvBoard }, + NvParamKey { key: 49880, name: "NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT", region: NvBoard }, + NvParamKey { key: 49888, name: "NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT", region: NvBoard }, + NvParamKey { key: 49896, name: "NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT", region: NvBoard }, + NvParamKey { key: 49904, name: "NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ", region: NvBoard }, + NvParamKey { key: 49912, name: "NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ", region: NvBoard }, + NvParamKey { key: 49920, name: "NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ", region: NvBoard }, + NvParamKey { key: 49928, name: "NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ", region: NvBoard }, + NvParamKey { key: 49936, name: "NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE", region: NvBoard }, + NvParamKey { key: 49944, name: "NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE", region: NvBoard }, + NvParamKey { key: 49952, name: "NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO", region: NvBoard }, + NvParamKey { key: 49960, name: "NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL", region: NvBoard }, + NvParamKey { key: 49968, name: "NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS", region: NvBoard }, + NvParamKey { key: 49976, name: "NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD", region: NvBoard }, + NvParamKey { key: 49984, name: "NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE", region: NvBoard }, + NvParamKey { key: 49992, name: "NV_SI_RO_BOARD_S0_PCIE_CLK_CFG", region: NvBoard }, + NvParamKey { key: 50000, name: "NV_SI_RO_BOARD_S0_RCA4_CFG", region: NvBoard }, + NvParamKey { key: 50008, name: "NV_SI_RO_BOARD_S0_RCA5_CFG", region: NvBoard }, + NvParamKey { key: 50016, name: "NV_SI_RO_BOARD_S0_RCA6_CFG", region: NvBoard }, + NvParamKey { key: 50024, name: "NV_SI_RO_BOARD_S0_RCA7_CFG", region: NvBoard }, + NvParamKey { key: 50032, name: "NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50040, name: "NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50048, name: "NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50056, name: "NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50064, name: "NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50072, name: "NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50080, name: "NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50088, name: "NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50096, name: "NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50104, name: "NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50112, name: "NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50120, name: "NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50128, name: "NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50136, name: "NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50144, name: "NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50152, name: "NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50160, name: "NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50168, name: "NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50176, name: "NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50184, name: "NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50192, name: "NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50200, name: "NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50208, name: "NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50216, name: "NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50224, name: "NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50232, name: "NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50240, name: "NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50248, name: "NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50256, name: "NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50264, name: "NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50272, name: "NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50280, name: "NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50288, name: "NV_SI_RO_BOARD_S1_PCIE_CLK_CFG", region: NvBoard }, + NvParamKey { key: 50296, name: "NV_SI_RO_BOARD_S1_RCA4_CFG", region: NvBoard }, + NvParamKey { key: 50304, name: "NV_SI_RO_BOARD_S1_RCA5_CFG", region: NvBoard }, + NvParamKey { key: 50312, name: "NV_SI_RO_BOARD_S1_RCA6_CFG", region: NvBoard }, + NvParamKey { key: 50320, name: "NV_SI_RO_BOARD_S1_RCA7_CFG", region: NvBoard }, + NvParamKey { key: 50328, name: "NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50336, name: "NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50344, name: "NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50352, name: "NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50360, name: "NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50368, name: "NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50376, name: "NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50384, name: "NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50392, name: "NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50400, name: "NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50408, name: "NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50416, name: "NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50424, name: "NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50432, name: "NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50440, name: "NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50448, name: "NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50456, name: "NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50464, name: "NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50472, name: "NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50480, name: "NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50488, name: "NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50496, name: "NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50504, name: "NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50512, name: "NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50520, name: "NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50528, name: "NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50536, name: "NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50544, name: "NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50552, name: "NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD", region: NvBoard }, + NvParamKey { key: 50560, name: "NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL", region: NvBoard }, + NvParamKey { key: 50568, name: "NV_SI_RO_BOARD_SX_PHY_CFG_SETTING", region: NvBoard }, + NvParamKey { key: 50576, name: "NV_SI_RO_BOARD_DDR_PHY_DC_CLK", region: NvBoard }, + NvParamKey { key: 50584, name: "NV_SI_RO_BOARD_DDR_PHY_DC_DATA", region: NvBoard }, + NvParamKey { key: 50592, name: "NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET", region: NvBoard }, + NvParamKey { key: 50600, name: "NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET", region: NvBoard }, + NvParamKey { key: 50608, name: "NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET", region: NvBoard }, + NvParamKey { key: 50616, name: "NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET", region: NvBoard }, + NvParamKey { key: 50624, name: "NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET", region: NvBoard }, + NvParamKey { key: 50632, name: "NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET", region: NvBoard }, + NvParamKey { key: 50640, name: "NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET", region: NvBoard }, + NvParamKey { key: 50648, name: "NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET", region: NvBoard }, + NvParamKey { key: 50656, name: "NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD", region: NvBoard }, + NvParamKey { key: 50664, name: "NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US", region: NvBoard }, + NvParamKey { key: 50672, name: "NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV", region: NvBoard }, + NvParamKey { key: 50680, name: "NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN", region: NvBoard }, + NvParamKey { key: 50688, name: "NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME", region: NvBoard }, + NvParamKey { key: 50696, name: "NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US", region: NvBoard }, + NvParamKey { key: 50704, name: "NV_SI_RO_BOARD_PCIE_AER_FW_FIRST", region: NvBoard }, + NvParamKey { key: 50712, name: "NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS", region: NvBoard }, + NvParamKey { key: 50720, name: "NV_SI_RO_BOARD_TPM_DISABLE", region: NvBoard }, + NvParamKey { key: 50728, name: "NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN", region: NvBoard }, + NvParamKey { key: 50736, name: "NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN", region: NvBoard }, + NvParamKey { key: 50744, name: "NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN", region: NvBoard }, + NvParamKey { key: 50752, name: "NV_SI_RO_BOARD_PCIE_HP_DISABLE", region: NvBoard }, + NvParamKey { key: 50760, name: "NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT", region: NvBoard }, + NvParamKey { key: 50768, name: "NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS", region: NvBoard }, + NvParamKey { key: 50776, name: "NV_SI_RO_BOARD_CUST_SPM_LOCATION", region: NvBoard }, + NvParamKey { key: 50784, name: "NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW", region: NvBoard }, + NvParamKey { key: 50792, name: "NV_SI_RO_BOARD_RAS_DDR_CE_TH1", region: NvBoard }, + NvParamKey { key: 50800, name: "NV_SI_RO_BOARD_RAS_DDR_CE_TH2", region: NvBoard }, + NvParamKey { key: 50808, name: "NV_SI_RO_BOARD_RAS_DDR_CE_THC", region: NvBoard }, + NvParamKey { key: 50816, name: "NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_20GPRESET", region: NvBoard }, + NvParamKey { key: 50824, name: "NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_20GPRESET", region: NvBoard }, + NvParamKey { key: 50832, name: "NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_25GPRESET", region: NvBoard }, + NvParamKey { key: 50840, name: "NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_25GPRESET", region: NvBoard }, + NvParamKey { key: 50848, name: "NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50856, name: "NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50864, name: "NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50872, name: "NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50880, name: "NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50888, name: "NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50896, name: "NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50904, name: "NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50912, name: "NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50920, name: "NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50928, name: "NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50936, name: "NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50944, name: "NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50952, name: "NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G3PRESET", region: NvBoard }, + NvParamKey { key: 50960, name: "NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50968, name: "NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50976, name: "NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50984, name: "NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 50992, name: "NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51000, name: "NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51008, name: "NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51016, name: "NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51024, name: "NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51032, name: "NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51040, name: "NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51048, name: "NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51056, name: "NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51064, name: "NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G4PRESET", region: NvBoard }, + NvParamKey { key: 51072, name: "NV_SI_RO_BOARD_RAS_FLAGS", region: NvBoard }, + NvParamKey { key: 51080, name: "NV_SI_RO_BOARD_DDR_PROGRESS_LOG_CTRL", region: NvBoard }, + NvParamKey { key: 51088, name: "NV_SI_RO_BOARD_2P_ALI_CE_MASK_THRESHOLD", region: NvBoard }, + NvParamKey { key: 51096, name: "NV_SI_RO_BOARD_2P_ALI_CE_MASK_INTERVAL", region: NvBoard }, + NvParamKey { key: 51104, name: "NV_SI_RO_BOARD_RAS_2P_CE_FILTER", region: NvBoard }, + NvParamKey { key: 51112, name: "NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD_EN", region: NvBoard }, + NvParamKey { key: 51120, name: "NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO1", region: NvBoard }, + NvParamKey { key: 51128, name: "NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_TO2", region: NvBoard }, + NvParamKey { key: 51136, name: "NV_SI_RO_BOARD_PCIE_AER_CE_THRESHOLD", region: NvBoard }, + NvParamKey { key: 51144, name: "NV_SI_RO_BOARD_PCIE_AER_CE_INTERVAL", region: NvBoard }, + NvParamKey { key: 51152, name: "NV_SI_RO_BOARD_I2C_RCA_VRD_VOUT_FORMAT", region: NvBoard }, + NvParamKey { key: 51160, name: "NV_SI_RO_BOARD_CCIX_MODE_OVERWRITE", region: NvBoard }, + NvParamKey { key: 51168, name: "NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_MARGIN_MV", region: NvBoard }, + NvParamKey { key: 51176, name: "NV_SI_RO_BOARD_2P_DPLL", region: NvBoard }, + NvParamKey { key: 51184, name: "NV_SI_RO_BOARD_RC_DOMAIN_CTRL", region: NvBoard }, + NvParamKey { key: 51192, name: "NV_SI_RO_BOARD_PCIE_SRIS_MODE", region: NvBoard }, +] + +// A key the header does not define is its number, never the nearest name. +type NvParamKeyReading + = NvParamKeyDefined { key: NvParamKey } + | NvParamKeyUndefined { key: Int } + +fn nvparam_key_text(r: NvParamKeyReading) -> String { + match r { + NvParamKeyDefined { key: k } => k.name as String + NvParamKeyUndefined { key: n } => concat("key ", to_string(n), " (not defined in NVParamDef.h)") + } +} + +// The key table as an index -- the one key-to-name route: built once per caller and queried per key, +// rather than scanning all rows for every key. +fn nvparam_key_index() -> Map { + fold(nvparam_keys, init: empty_map(), f: (acc, k) => map_insert(m: acc, key: k.key, value: k)) +} + +fn nvparam_key_in(index: Map, key: Int) -> NvParamKeyReading { + match map_lookup(m: index, key: key) { + Present { value: k } => NvParamKeyDefined { key: k } + Absent => NvParamKeyUndefined { key: key } + } +} diff --git a/dag/gunbc/extdeps_scope_frontier.dag b/dag/gunbc/extdeps_scope_frontier.dag index 5da8a8ca6d2..2f4528ed894 100644 --- a/dag/gunbc/extdeps_scope_frontier.dag +++ b/dag/gunbc/extdeps_scope_frontier.dag @@ -273,6 +273,7 @@ data scope_carrier_paths: List = [ "dag/extdeps/ampere/oem_sel.dag", "dag/extdeps/ampere/smpro_register.dag", "dag/extdeps/ampere/smpro_internal_error.dag", + "dag/extdeps/ampere/nvparam.dag", "dag/extdeps/ampere/mt_collins_product_brief/subject.dag", "dag/extdeps/ampere/mt_collins_product_brief/memory_population.dag", "dag/extdeps/ampere/mt_collins_getting_started_guide/subject.dag", diff --git a/dag/gunbc/machine_intake/ampere_nvparam_console_observation.dag b/dag/gunbc/machine_intake/ampere_nvparam_console_observation.dag new file mode 100644 index 00000000000..f854dd5363a --- /dev/null +++ b/dag/gunbc/machine_intake/ampere_nvparam_console_observation.dag @@ -0,0 +1,181 @@ +module gunbc.machine_intake_ampere_nvparam_console_observation + +import v2.std.algebra { filter, any, list_reverse } +import std.algebra { Cons } +import std.measure { byte_size_count } +import std.types { Bool, Int, List, Map, NonEmptyStr, String } +import std.algebra { trim } +import v2.std.optional { Present } +import extdeps.numeric.base16 { base16_word_value } +import extdeps.ampere.nvparam { + NvParamRegion, NvPreboot, NvManufacturing, NvUser, NvBoard, + NvParamKey, NvParamKeyReading, NvParamKeyDefined, NvParamKeyUndefined, nvparam_key_index, nvparam_key_in, nvparam_key_text, nvparam_size, nvparam_region_start, nvparam_region_max, +} +import gunbc.machine_intake_ampere_dram_console_observation { ampere_dram_console_line } + +// THE NVPARAM DUMP A BOOT PRINTS, READ INTO NAMED SETTINGS. The firmware's PrintNVRAM +// (edk2-platforms@2170c80c Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c) walks +// each region and, for every key NVParamGet answers, prints a section header once -- +// "Pre-boot Configuration Setting:", "Manufacturer Configuration Setting:", "User Configuration +// Setting:", "Board Configuration Setting:" -- then one row per key in the format +// " %04X: 0x%X (%d)\n": the key in hex, the value in hex, the value in decimal. +// +// The KEY's name comes from extdeps.ampere.nvparam (NVParamDef.h); a key the header does not define +// stays its number. What a VALUE means is not stated by any public source and is not decoded. +// +// The loop steps Idx by NVPARAM_SIZE from each region's start, so a printed key is always on the +// 8-byte stride; an off-stride key is malformed, while an on-stride key the header does not name +// stays an explicit unknown. +// +// A ROW IS READ ONLY INSIDE A SECTION, and a section ends at any line that is not a row, so an +// unrelated indented line elsewhere in a capture is never taken for a setting. A row whose hex and +// decimal renderings disagree, or whose key lies outside the section's region, is MALFORMED and +// kept as its text, never coerced. + +type NvParamSetting { + region: NvParamRegion + key: NvParamKeyReading + value: Int +} + +type NvParamMalformedRow { + region: NvParamRegion + line: String + reason: NonEmptyStr +} + +type NvParamConsoleObservation { + settings: List + malformed: List +} + +fn nvparam_section_of(line: String) -> NvParamRegion? { + let t = trim(line) + if t == "Pre-boot Configuration Setting:" { Present { value: NvPreboot } } + else if t == "Manufacturer Configuration Setting:" { Present { value: NvManufacturing } } + else if t == "User Configuration Setting:" { Present { value: NvUser } } + else if t == "Board Configuration Setting:" { Present { value: NvBoard } } + else { none } +} + +// Hex through the corpus's one bounded base-16 word authority. Fifteen digits is that authority's +// cap; the UINT32 bound on a value is checked separately, so 0x100000000 parses and is then refused. +fn hex_of(text: String) -> Int? { + base16_word_value(word: text, max_digits: 15) +} + +// PrintNVRAM's Val is a UINT32 printed with %X and with %d: the hex is 0..0xFFFFFFFF and the decimal +// is that same 32 bits read as signed, so a value at or above 2^31 prints negative. +data nvparam_uint32_max: Int = 4294967295 + +fn nvparam_signed32_rendering(value: Int) -> Int { + if value >= 2147483648 { value - 4294967296 } else { value } +} + +// " KKKK: 0xV (D)" -> (key, value), or why it is not one. +type NvParamRowRead + = NvParamRowParsed { key: Int, value: Int } + | NvParamRowRejected { reason: NonEmptyStr } + | NvParamNotARow + +fn nvparam_row_of(line: String) -> NvParamRowRead { + if !starts_with(s: line, prefix: " ") { NvParamNotARow } else { + let parts = split(s: trim(line), delimiter: ": 0x") + if count(parts) != 2 { NvParamNotARow } else { + let key_text = match parts.first() { Present { value: k } => k Absent => "" } + let rest = match parts.skip(n: 1).first() { Present { value: r } => r Absent => "" } + let value_parts = split(s: rest, delimiter: " (") + let hex_text = match value_parts.first() { Present { value: h } => h Absent => "" } + let dec_text = match value_parts.skip(n: 1).first() { Present { value: d } => join(split(s: d, delimiter: ")"), "") Absent => "" } + match hex_of(text: key_text) { + Absent => NvParamNotARow + Present { value: key } => match hex_of(text: hex_text) { + Absent => NvParamRowRejected { reason: "the value is not hex" } + Present { value: v } => match parse_int(s: dec_text) { + Absent => NvParamRowRejected { reason: "the decimal rendering is missing or not a number" } + Present { value: d } => if v > nvparam_uint32_max { NvParamRowRejected { reason: "the value exceeds the UINT32 Val PrintNVRAM prints" } } + else if d == nvparam_signed32_rendering(value: v) { NvParamRowParsed { key: key, value: v } } + else { NvParamRowRejected { reason: "the decimal is not the %d (signed 32-bit) rendering of the hex value" } } + } + } + } + } + } +} + +type NvParamReadState { + index: Map + section: NvParamRegion? + observation: NvParamConsoleObservation +} + +// The fold accumulates newest-first (one cons per row) and ampere_nvparam_console_observation +// reverses once at the end: appending per row would copy the accumulator every row. +fn with_setting(o: NvParamConsoleObservation, s: NvParamSetting) -> NvParamConsoleObservation { + NvParamConsoleObservation { settings: Cons { head: s, tail: o.settings }, malformed: o.malformed } +} + +fn with_malformed(o: NvParamConsoleObservation, m: NvParamMalformedRow) -> NvParamConsoleObservation { + NvParamConsoleObservation { settings: o.settings, malformed: Cons { head: m, tail: o.malformed } } +} + +// Outside a section only a header can matter, and every header ends "Configuration Setting:", so a +// line without that text is passed over before it is normalized: a whole boot capture costs one +// substring test per line until the dump begins. +fn nvparam_read_step(state: NvParamReadState, raw: String) -> NvParamReadState { + match state.section { + Absent => if !raw.contains("Configuration Setting:") { state } else { nvparam_read_line(state: state, raw: raw) } + Present { value: _ } => nvparam_read_line(state: state, raw: raw) + } +} + +fn nvparam_read_line(state: NvParamReadState, raw: String) -> NvParamReadState { + let line = ampere_dram_console_line(raw: raw) + match nvparam_section_of(line: line) { + Present { value: r } => NvParamReadState { index: state.index, section: Present { value: r }, observation: state.observation } + Absent => match state.section { + Absent => state + Present { value: region } => match nvparam_row_of(line: line) { + NvParamNotARow => NvParamReadState { index: state.index, section: none, observation: state.observation } + NvParamRowRejected { reason: why } => NvParamReadState { index: state.index, section: state.section, observation: with_malformed(o: state.observation, m: NvParamMalformedRow { region: region, line: line, reason: why }) } + NvParamRowParsed { key: k, value: v } => { + let base = nvparam_region_start(r: region) + if k < base || k > nvparam_region_max(r: region) { + NvParamReadState { index: state.index, section: state.section, observation: with_malformed(o: state.observation, m: NvParamMalformedRow { region: region, line: line, reason: "the key lies outside the START..MAX range PrintNVRAM walks for this section's region" }) } + } else if (k - base) % (byte_size_count(b: nvparam_size) as Int) != 0 { + NvParamReadState { index: state.index, section: state.section, observation: with_malformed(o: state.observation, m: NvParamMalformedRow { region: region, line: line, reason: "the key is not on the 8-byte NVPARAM_SIZE stride from its region base" }) } + } else { + NvParamReadState { index: state.index, section: state.section, observation: with_setting(o: state.observation, s: NvParamSetting { region: region, key: nvparam_key_in(index: state.index, key: k), value: v }) } + } + } + } + } + } +} + +fn ampere_nvparam_console_observation(lines: List) -> NvParamConsoleObservation { + let none_set: List = [] + let none_bad: List = [] + let rev = fold(lines, init: NvParamReadState { index: nvparam_key_index(), section: none, observation: NvParamConsoleObservation { settings: none_set, malformed: none_bad } }, f: (s, l) => nvparam_read_step(state: s, raw: l)).observation + NvParamConsoleObservation { settings: list_reverse(xs: rev.settings), malformed: list_reverse(xs: rev.malformed) } +} + +fn nvparam_setting_text(s: NvParamSetting) -> String { + concat(nvparam_key_text(r: s.key), " = ", to_string(s.value)) +} + +fn nvparam_region_label(r: NvParamRegion) -> String { + match r { NvPreboot => "pre-boot" NvManufacturing => "manufacturer" NvUser => "user" NvBoard => "board" } +} + +// The dump as the boot bundle renders it: every setting by name, then every malformed row with its +// reason. A capture that printed no NVPARAM section says so rather than rendering an empty list. +fn ampere_nvparam_console_text(o: NvParamConsoleObservation) -> String { + if count(o.settings) == 0 && count(o.malformed) == 0 { "NVPARAM: no Configuration Setting section in this capture" } else { + join(concat( + [concat("NVPARAM: ", to_string(count(o.settings)), " setting(s), ", to_string(count(o.malformed)), " malformed row(s) (edk2-platforms PrintNVRAM, keys named by NVParamDef.h)")], + concat( + map(o.settings, s => concat(" ", nvparam_region_label(r: s.region), " ", nvparam_setting_text(s: s))), + map(o.malformed, m => concat(" MALFORMED ", nvparam_region_label(r: m.region), " row [", trim(m.line), "]: ", m.reason as String)))), "\n") + } +} diff --git a/dag/gunbc/machine_intake/mtcollins1_boot_diagnostic_bundle.dag b/dag/gunbc/machine_intake/mtcollins1_boot_diagnostic_bundle.dag index b1a954d5ab7..6cfc5ba4084 100644 --- a/dag/gunbc/machine_intake/mtcollins1_boot_diagnostic_bundle.dag +++ b/dag/gunbc/machine_intake/mtcollins1_boot_diagnostic_bundle.dag @@ -49,6 +49,7 @@ import gunbc.machine_intake_ampere_dram_console_observation { AmpereDramConsoleObservation, ampere_dram_console_observation, ampere_dram_findings, ampere_dram_console_text, } import gunbc.machine_intake_kernel_module_decompression_observation { KernelModuleDecompressionObservation, kernel_module_decompression_observation, kernel_module_decompression_text, kernel_module_decompression_findings } +import gunbc.machine_intake_ampere_nvparam_console_observation { NvParamConsoleObservation, ampere_nvparam_console_observation, ampere_nvparam_console_text } import gunbc.machine_intake_ampere_socket_console_observation { AmpereSocketConsoleObservation, AmpereSummaryObserved, AmpereSummaryNotPrinted, AmpereSocketReferenceComparison, ampere_socket_console_observation, ampere_socket_console_text, ampere_socket_reference_comparison, ampere_socket_reference_comparison_text, @@ -357,7 +358,7 @@ type InventoryReading { // those bytes would under-count multi-byte console output. The size is taken before the content is // read, so a capture over the bound is reported without being loaded. type ConsoleReading - = ConsoleRetained { path: NonEmptyStr, size: ByteSize, lines: Int, firmware: FirmwareConsoleReport, dram: AmpereDramConsoleObservation, sockets: AmpereSocketConsoleObservation, against_reference: AmpereSocketReferenceComparison, modules: KernelModuleDecompressionObservation } + = ConsoleRetained { path: NonEmptyStr, size: ByteSize, lines: Int, firmware: FirmwareConsoleReport, dram: AmpereDramConsoleObservation, sockets: AmpereSocketConsoleObservation, against_reference: AmpereSocketReferenceComparison, modules: KernelModuleDecompressionObservation, nvparam: NvParamConsoleObservation } | ConsoleExceedsBound { path: NonEmptyStr, size: ByteSize, bound: ByteSize } | ConsoleNotRetained { path: NonEmptyStr } | ConsoleUnread { path: NonEmptyStr, detail: String } @@ -1091,7 +1092,7 @@ fn socket_summary_findings(o: AmpereSocketConsoleObservation) -> List { fn console_findings(c: ConsoleReading) -> List { match c { - ConsoleRetained { path: _, size: _, lines: _, firmware: _, dram: d, sockets: o, against_reference: _, modules: m } => concat(ampere_dram_findings(observation: d, expected_sockets: mtcollins1_census_sockets()), concat(socket_summary_findings(o: o), kernel_module_decompression_findings(o: m))) + ConsoleRetained { path: _, size: _, lines: _, firmware: _, dram: d, sockets: o, against_reference: _, modules: m, nvparam: _ } => concat(ampere_dram_findings(observation: d, expected_sockets: mtcollins1_census_sockets()), concat(socket_summary_findings(o: o), kernel_module_decompression_findings(o: m))) ConsoleExceedsBound { path: _, size: _, bound: _ } => [] ConsoleNotRetained { path: _ } => [] ConsoleUnread { path: _, detail: _ } => [] @@ -1448,8 +1449,8 @@ fn firmware_report_text(report: FirmwareConsoleReport) -> String { fn console_text(c: ConsoleReading) -> String { match c { - ConsoleRetained { path: p, size: b, lines: n, firmware: f, dram: d, sockets: o, against_reference: cmp, modules: m } => - concat("capture ", p as String, " retained in this artifact: ", to_string(byte_size_count(b: b)), " bytes (stat), ", to_string(n), " line(s), within the ", to_string(byte_size_count(b: mtcollins1_boot_console_bound)), "-byte bound; ", firmware_report_text(report: f), "\n", ampere_dram_console_text(observation: d, expected_sockets: mtcollins1_census_sockets()), "\n", ampere_socket_console_text(o: o), ampere_socket_reference_comparison_text(c: cmp), "\n", kernel_module_decompression_text(o: m)) + ConsoleRetained { path: p, size: b, lines: n, firmware: f, dram: d, sockets: o, against_reference: cmp, modules: m, nvparam: nv } => + concat("capture ", p as String, " retained in this artifact: ", to_string(byte_size_count(b: b)), " bytes (stat), ", to_string(n), " line(s), within the ", to_string(byte_size_count(b: mtcollins1_boot_console_bound)), "-byte bound; ", firmware_report_text(report: f), "\n", ampere_dram_console_text(observation: d, expected_sockets: mtcollins1_census_sockets()), "\n", ampere_socket_console_text(o: o), ampere_socket_reference_comparison_text(c: cmp), "\n", kernel_module_decompression_text(o: m), "\n", ampere_nvparam_console_text(o: nv)) ConsoleExceedsBound { path: p, size: b, bound: bound } => concat("capture ", p as String, " is ", to_string(byte_size_count(b: b)), " bytes (stat), OVER the ", to_string(byte_size_count(b: bound)), "-byte bound; the collector does not truncate, so the artifact carries it whole") ConsoleNotRetained { path: p } => @@ -2148,6 +2149,7 @@ fn mtcollins1_boot_console_reading(path: String, size: ByteSize, capture: String sockets: sockets, against_reference: ampere_socket_reference_comparison(reference_path: mtcollins1_census_sol_artifact_path, reference_text: reference.text, read_ok: reference.ok, read_error: reference.error, subject: sockets), modules: kernel_module_decompression_observation(lines: lines), + nvparam: ampere_nvparam_console_observation(lines: lines), } } } diff --git a/dag/test/claim/machine_intake/ampere_nvparam_console_observation_witness_test.dag b/dag/test/claim/machine_intake/ampere_nvparam_console_observation_witness_test.dag new file mode 100644 index 00000000000..6cd3115e431 --- /dev/null +++ b/dag/test/claim/machine_intake/ampere_nvparam_console_observation_witness_test.dag @@ -0,0 +1,140 @@ +module test.claim.machine_intake.ampere_nvparam_console_observation_witness_test + +import std.types { Bool, Int, List, String } +import v2.std.live_tree { LiveTreeDisposition, ReadsLiveTree } +import v2.std.optional { Present } +import v2.std.algebra { filter } +import extdeps.ampere.nvparam { NvParamKeyDefined, NvParamKeyUndefined, nvparam_key_in, nvparam_key_index, nvparam_keys } +import gunbc.machine_intake_ampere_nvparam_console_observation { + NvParamConsoleObservation, NvParamSetting, ampere_nvparam_console_observation, ampere_nvparam_console_text, +} +import gunbc.machine_intake_mtcollins1_sixteen_module_restore_observation { mtcollins1_run_a_sparse_reference_capture } + +data live_tree_disposition: LiveTreeDisposition = ReadsLiveTree + +// ── the key table (extdeps.ampere.nvparam) ────────────────────────────────────────────────────── + +fn key_named(key: Int, name: String) -> Bool { + match nvparam_key_in(index: nvparam_key_index(), key: key) { NvParamKeyDefined { key: k } => (k.name as String) == name NvParamKeyUndefined { key: _ } => false } +} + +test fn the_header_keys_resolve_by_region_base_plus_eight_per_parameter() -> Bool { + key_named(key: 16, name: "NV_SI_FAILSAFE_RETRY") + && key_named(key: 32800, name: "NV_SI_WDT_BIOS_EXP_MINS") + && key_named(key: 33056, name: "NV_SI_SEC_WDT_BIOS_EXP_MINS") + && key_named(key: 49184, name: "NV_SI_RO_BOARD_S0_DIMM_AVAIL") + && key_named(key: 49192, name: "NV_SI_RO_BOARD_S1_DIMM_AVAIL") + && key_named(key: 50552, name: "NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD") + && count(nvparam_keys) == 513 +} + +test fn red_a_key_the_header_does_not_define_is_its_number() -> Bool { + match nvparam_key_in(index: nvparam_key_index(), key: 32801) { NvParamKeyUndefined { key: n } => n == 32801 NvParamKeyDefined { key: _ } => false } +} + +// The value a dump reported for one named key, if it carried it (a reading for this witness only). +fn nvparam_setting_named(o: NvParamConsoleObservation, name: String) -> Int? { + match filter(o.settings, s => match s.key { NvParamKeyDefined { key: k } => (k.name as String) == name NvParamKeyUndefined { key: _ } => false }).first() { + Present { value: s } => Present { value: s.value } + Absent => none + } +} + +fn has_value(o: NvParamConsoleObservation, name: String, v: Int) -> Bool { + match nvparam_setting_named(o: o, name: name) { Present { value: x } => x == v Absent => false } +} + +fn carries(o: NvParamConsoleObservation, name: String) -> Bool { + match nvparam_setting_named(o: o, name: name) { Present { value: _ } => true Absent => false } +} + +// ── the dump grammar, over supplied lines ─────────────────────────────────────────────────────── + +test fn rows_are_read_only_inside_a_section() -> Bool { + let o = ampere_nvparam_console_observation(lines: [" 8020: 0x5 (5)\r", "User Configuration Setting:\r", " 8020: 0x5 (5)\r", " 8120: 0x12C (300)\r", "Board Configuration Setting:\r", " C020: 0xFFFF (65535)\r", "next line\r", " C028: 0xFFFF (65535)\r"]) + count(o.settings) == 3 + && has_value(o: o, name: "NV_SI_SEC_WDT_BIOS_EXP_MINS", v: 300) + && !carries(o: o, name: "NV_SI_RO_BOARD_S1_DIMM_AVAIL") +} + +// %d of a UINT32 prints a negative number past 2^31: that is agreement, not disagreement. +test fn a_negative_decimal_rendering_of_a_large_value_agrees() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["Board Configuration Setting:", " C080: 0xFFFFFF01 (-255)"]) + count(o.settings) == 1 && count(o.malformed) == 0 +} + +test fn red_hex_and_decimal_that_disagree_are_malformed_not_a_setting() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["User Configuration Setting:", " 8020: 0x5 (6)"]) + count(o.settings) == 0 && count(o.malformed) == 1 +} + +test fn red_a_key_outside_its_sections_region_is_malformed() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["User Configuration Setting:", " C020: 0xFFFF (65535)"]) + count(o.settings) == 0 && count(o.malformed) == 1 +} + +test fn red_a_value_past_uint32_is_malformed() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["User Configuration Setting:", " 8020: 0x100000000 (0)"]) + count(o.settings) == 0 && count(o.malformed) == 1 +} + +// A large value printed with its UNSIGNED decimal is not what %d prints. +test fn red_an_unsigned_decimal_for_a_large_value_is_malformed() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["Board Configuration Setting:", " C080: 0xFFFFFF01 (4294967041)"]) + count(o.settings) == 0 && count(o.malformed) == 1 +} + +test fn red_an_off_stride_key_is_malformed() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["User Configuration Setting:", " 8021: 0x5 (5)"]) + count(o.settings) == 0 && count(o.malformed) == 1 +} + +// On the stride and inside NV_MANU_PARAM_START..MAX, but not named by the header (0x41A8 is one of +// the header's two manufacturing gaps): kept, as an explicit unknown. +test fn an_on_stride_unlisted_key_is_an_explicit_unknown() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["Manufacturer Configuration Setting:", " 41A8: 0x1 (1)"]) + count(o.settings) == 1 && count(o.malformed) == 0 + && (match o.settings.first() { Present { value: st } => match st.key { NvParamKeyUndefined { key: n } => n == 16808 NvParamKeyDefined { key: _ } => false } Absent => false }) +} + +// RED: past NV_BOARD_PARAM_MAX (0xC7F8) the key is outside the range PrintNVRAM walks. +test fn red_a_key_past_the_regions_param_max_is_malformed() -> Bool { + let o = ampere_nvparam_console_observation(lines: ["Board Configuration Setting:", " C800: 0x1 (1)"]) + count(o.settings) == 0 && count(o.malformed) == 1 +} + +test fn a_capture_without_a_dump_says_so() -> Bool { + ampere_nvparam_console_text(o: ampere_nvparam_console_observation(lines: ["UEFI firmware booting"])) == "NVPARAM: no Configuration Setting section in this capture" +} + +// ── the real capture (run A, committed artifact, read by path) ────────────────────────────────── + +// The archive renders each console CR as the two printable characters `^M` (no 0x0d byte; see +// mtcollins1_sixteen_module_restore_witness_test console_cr_rendering, measured on these files), so +// the rendering is removed per line before the console grammar sees it. +fn without_rendered_cr(line: String) -> String { + if line.ends_with("^M") { line.substring(start: 0, end: line.length() - 2) } else { line } +} + +// THE COMMITTED BYTES: THE FIRST FIFTY LINES FROM THE FIRST SECTION HEADER -- the whole user section +// and the first board rows, including the keys asserted below. The claim establishes the ROUTE (real +// bytes through the real grammar, key index and rendering); every further row is the same route again, +// so the slice keeps the claim inside the floor's new-witness step budget without supplying a byte. +fn run_a_observation() -> NvParamConsoleObservation { + let content = Filesystem.Read(path: mtcollins1_run_a_sparse_reference_capture.artifact_path as String).content + let from_dump = concat("User Configuration Setting:", join(content.split(sep: "User Configuration Setting:").skip(n: 1), "User Configuration Setting:")) + ampere_nvparam_console_observation(lines: map(from_dump.split(sep: "\n").take(n: 50), l => without_rendered_cr(line: l))) +} + +// The inhabitance claim: the committed boot's dump reaches the real grammar, the real key table and +// the rendering the boot bundle prints -- one parse, both readings. +test fn run_a_dump_reads_into_named_settings_and_renders_them() -> Bool { + let o = run_a_observation() + let t = ampere_nvparam_console_text(o: o) + count(o.settings) > 40 && count(o.malformed) == 0 + && has_value(o: o, name: "NV_SI_WDT_BIOS_EXP_MINS", v: 5) + && has_value(o: o, name: "NV_SI_SEC_WDT_BIOS_EXP_MINS", v: 300) + && has_value(o: o, name: "NV_SI_RO_BOARD_VENDOR", v: 52538) + && has_value(o: o, name: "NV_SI_RO_BOARD_S0_DIMM_AVAIL", v: 65535) + && t.contains("user NV_SI_WDT_BIOS_EXP_MINS = 5") && t.contains("board NV_SI_RO_BOARD_VENDOR = 52538") +} diff --git a/dag/test/claim/machine_intake/kernel_module_decompression_observation_witness_test.dag b/dag/test/claim/machine_intake/kernel_module_decompression_observation_witness_test.dag index cbce7165301..3a2a98c726d 100644 --- a/dag/test/claim/machine_intake/kernel_module_decompression_observation_witness_test.dag +++ b/dag/test/claim/machine_intake/kernel_module_decompression_observation_witness_test.dag @@ -203,7 +203,7 @@ test fn unrelated_text_is_not_a_record() -> Bool { test fn the_retained_console_reading_carries_the_refusal() -> Bool { let capture = join(failed_attempt_excerpt, "\n") match mtcollins1_boot_console_reading(path: "artifacts/mtcollins1-boot-sol.capture", size: byte_size(count: 10), capture: concat(capture, "\n"), read_ok: true, read_error: "", reference: ReferenceCaptureRead { text: "", ok: false, error: "not supplied" }) { - ConsoleRetained { path: _, size: _, lines: _, firmware: _, dram: _, sockets: _, against_reference: _, modules: m } => + ConsoleRetained { path: _, size: _, lines: _, firmware: _, dram: _, sockets: _, against_reference: _, modules: m, nvparam: _ } => match m { RefusalRecorded { refusals: rs, unparsed_refusal_records: _, insert_failures: _, unparsed_insert_records: _, identity: RefusalIdentityUnread } => count(rs) == 2 _ => false } _ => false } diff --git a/dag/test/claim/machine_intake/mtcollins1_boot_diagnostic_bundle_witness_test.dag b/dag/test/claim/machine_intake/mtcollins1_boot_diagnostic_bundle_witness_test.dag index 4c6a5436918..da13446611e 100644 --- a/dag/test/claim/machine_intake/mtcollins1_boot_diagnostic_bundle_witness_test.dag +++ b/dag/test/claim/machine_intake/mtcollins1_boot_diagnostic_bundle_witness_test.dag @@ -462,7 +462,7 @@ test fn a_capture_outside_the_uploaded_glob_is_reported_not_retained() -> Bool { test fn a_retained_capture_reports_its_firmware_statement() -> Bool { let capture = "ERROR: Non-identical DIMM mixture NOT supported!\n" match mtcollins1_boot_console_reading(path: "/w/artifacts/mtcollins1-boot-sol.capture", size: byte_size(count: 51), capture: capture, read_ok: true, read_error: "", reference: no_reference) { - ConsoleRetained { path: _, size: b, lines: _, firmware: f, dram: _, sockets: _, against_reference: _, modules: _ } => (byte_size_count(b: b) as Int) == 51 && match f { TrainingRefusedByFirmware { statement: _, locus: _ } => true _ => false } + ConsoleRetained { path: _, size: b, lines: _, firmware: f, dram: _, sockets: _, against_reference: _, modules: _, nvparam: _ } => (byte_size_count(b: b) as Int) == 51 && match f { TrainingRefusedByFirmware { statement: _, locus: _ } => true _ => false } _ => false } } @@ -559,7 +559,7 @@ test fn a_supplied_reference_renders_its_differences() -> Bool { let reference = "UEFI RC version: 1.08\r\n Number of active sockets : 2\r\n Inter Socket Connection 0 : Width: x16 / Speed 25 GT/s\r\n Socket[0]: Core voltage : 1065\r\n Socket[1]: Core voltage : 1035\r\n" let capture = "UEFI RC version: 1.08\r\n Number of active sockets : 1\r\n Socket[0]: Core voltage : 1065\r\n" match mtcollins1_boot_console_reading(path: "artifacts/mtcollins1-boot-sol.capture", size: byte_size(count: 100), capture: capture, read_ok: true, read_error: "", reference: reference_of(text: reference)) { - ConsoleRetained { path: _, size: _, lines: _, firmware: _, dram: _, sockets: _, against_reference: _, modules: _ } => { + ConsoleRetained { path: _, size: _, lines: _, firmware: _, dram: _, sockets: _, against_reference: _, modules: _, nvparam: _ } => { let b = bundle_socket1_absent() let text = mtcollins1_boot_bundle_text(bundle: MtCollins1BootDiagnosticBundle { attempt: b.attempt, outcome: b.outcome, sel_before: b.sel_before, sel_after: b.sel_after, sdr_cache: b.sdr_cache, sensors: b.sensors, smpro: b.smpro, inventory: b.inventory, console: mtcollins1_boot_console_reading(path: "artifacts/mtcollins1-boot-sol.capture", size: byte_size(count: 100), capture: capture, read_ok: true, read_error: "", reference: reference_of(text: reference)), run: no_run(), screen: no_screen() })