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sync/atomic: CAS on ARM does not provide memory fence #7977
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We will need a way to test this. BTW, we can test it on linux, because src/sync/atomic/export_linux_arm_test.go exported generalCAS64 to tests on linux/arm, and we do have SMP linux machines. If we could make a test, say, running in less than 30s, I think it's worthwhile to enable it for -short tests. Labels changed: added release-go1.3maybe, repo-main. Status changed to Accepted. |
FTR, a comment by minux from https://golang.org/cl/91230048/: ----- src/pkg/runtime/asm_arm.s:579: BYTE $0xf3; BYTE $0xbf; BYTE $0x8f; BYTE $0x5b // DMB ISH DMB is only supported on ARMv7. for V6, we will need to use something like: mcr p15, 0, REG, c7, c10, 5 for dmb (REG is an ARM register that must contain 0). |
on linux, cas32 is always using kernel provided routine, so no problem there. for cas64, we have a three way choice: 1. for modern ones (>=3.1), cas64 will be handled by the kernel provided routine, 2. if we are running on ARMv6 or above on older kernels, we will use the generic LDREX/STREX based implementation, and we need DMB in this case, at least in theory. 3. if we are running on ARMv5E on older kernel, use lock-based cas64 emulation from runtime. in that case, the memory barrier should be provided by the mutex? on ARMv5E, cp15 isn't supported, but I don't think ARMv5 supports MP either. on ARMv6+, cp15 is supported, and depending on the kernel SMP configuration, dmb in the kernel provided cas64 primitive will either be replaced with a simple compiler memory barrier (asm (::"memory")), or it the real cp15 mcr instruction. So for SMP configurations, choice 1 and 2 shouldn't have any performance differences. Using DMB definitely have adverse performance impact on non-SMP ARMv6+ CPUs, but I guess we can't do any better (actually i think whether the lack of DMB is a problem or not depends on the implementation of the cpu) |
In attempting to swap out the darwin/arm builder for a 4th generation iPad (Apple A6X chip) I ran across this possibly-related error message:
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I'm a little worried about not fixing this for Go 1.5, because it may affect iOS. This can be fixed for iOS in a similar way to the linux fix. Because iOS always implies cgo, we can pass the darwin OSAtomicCompareAndSwap32Barrier symbol into the runtime and use it the way we do the linux-provided CAS. Does that seem reasonable? |
Here is the disassembly for armv7s version of OSAtomicCompareAndSwap64Barrier: I've verified that the arm64 version doesn't have barrier. We can just add DMB instruction to our CAS implementation. |
CL https://golang.org/cl/12950 mentions this issue. |
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