From 50cc73ea1ead874c7f2a7b7840df01f91cf807dd Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Tue, 3 Oct 2023 12:02:23 +0700 Subject: [PATCH 1/4] add basic support for BSCANE2, DCIRESET, ICAPE2, STARTUPE2 --- common/kernel/context.h | 20 +++++++++++++ xilinx/constids.inc | 15 ++++++++++ xilinx/external/nextpnr-xilinx-meta | 2 +- xilinx/fasm.cc | 45 +++++++++++++++++++++++++++++ xilinx/pack.cc | 1 + xilinx/pack.h | 3 ++ xilinx/pack_clocking_xc7.cc | 12 ++++++++ 7 files changed, 97 insertions(+), 1 deletion(-) diff --git a/common/kernel/context.h b/common/kernel/context.h index b4e7920d2..a243bd3d6 100644 --- a/common/kernel/context.h +++ b/common/kernel/context.h @@ -60,6 +60,26 @@ struct Context : Arch, DeterministicRNG delay_t getNetinfoRouteDelay(const NetInfo *net_info, const PortRef &sink) const; DelayQuad getNetinfoRouteDelayQuad(const NetInfo *net_info, const PortRef &sink) const; + bool net_is_constant(NetInfo *net, bool &value) + { + auto gnd = this->id("$PACKER_GND_NET"); + auto vcc = this->id("$PACKER_VCC_NET"); + if (net == nullptr) + return false; + if (net->name.in(gnd, vcc)) { + value = (net->name == vcc); + return true; + } else { + return false; + } + } + + bool net_is_constant(NetInfo *net) + { + bool unused; + return net_is_constant(net, unused); + } + // provided by router1.cc bool checkRoutedDesign() const; bool getActualRouteDelay(WireId src_wire, WireId dst_wire, delay_t *delay = nullptr, diff --git a/xilinx/constids.inc b/xilinx/constids.inc index 4f7119058..1a1e832b7 100644 --- a/xilinx/constids.inc +++ b/xilinx/constids.inc @@ -279,6 +279,9 @@ X(AREG) X(BEL) X(BITSLICE_CONTROL_BEL) X(BREG) +X(BSCAN) +X(BSCAN_BSCAN) +X(BSCANE2) X(BUFG) X(BUFG_BUFG) X(BUFG_PS) @@ -342,6 +345,8 @@ X(DATA_RATE) X(DATA_RATE_OQ) X(DATA_RATE_TQ) X(DATA_WIDTH) +X(DCIRESET) +X(DCIRESET_DCIRESET) X(DCITERMDISABLE) X(DCLK) X(DDLY) @@ -431,6 +436,10 @@ X(IBUFE3) X(IBUF_ANALOG) X(IBUF_IBUFDISABLE) X(IBUF_INTERMDISABLE) +X(ICAPE2) +X(ICAP) +X(ICAP_ICAP) +X(ICAP_WIDTH) X(IDATAIN) X(IDDR) X(IDDRE1) @@ -508,6 +517,7 @@ X(IS_S1_INVERTED) X(IS_SR_INVERTED) X(IS_S_INVERTED) X(IS_WCLK_INVERTED) +X(JTAG_CHAIN) X(LDCE) X(LDPE) X(LDPIPEEN) @@ -585,6 +595,7 @@ X(PLLE3_BASE) X(PLLE4_ADV) X(PLLE4_BASIC) X(PRE) +X(PROG_USR) X(PS8) X(PSCLK) X(PSEN) @@ -678,6 +689,9 @@ X(SRLC32E) X(SRTYPE) X(SRVAL_OQ) X(SRVAL_TQ) +X(STARTUPE2) +X(STARTUP) +X(STARTUP_STARTUP) X(SYSMONE1) X(SYSMONE4) X(T) @@ -704,6 +718,7 @@ X(TX_RST_DLY) X(T_OUT) X(URAM288_BASE) X(USE_DPORT) +X(USRCCLKO) X(VCC) X(VREF) X(VTC_RDY) diff --git a/xilinx/external/nextpnr-xilinx-meta b/xilinx/external/nextpnr-xilinx-meta index 772a3d520..9c57dc971 160000 --- a/xilinx/external/nextpnr-xilinx-meta +++ b/xilinx/external/nextpnr-xilinx-meta @@ -1 +1 @@ -Subproject commit 772a3d5204e82bbb1622f6a4d5d6d2fd32277bd3 +Subproject commit 9c57dc971444d16aa32d5293e10d60675f72fee6 diff --git a/xilinx/fasm.cc b/xilinx/fasm.cc index 92ac7cc51..ab5396a63 100644 --- a/xilinx/fasm.cc +++ b/xilinx/fasm.cc @@ -1157,6 +1157,50 @@ struct FasmBackend } } + void write_cfg() + { + for (auto &cell : ctx->cells) { + CellInfo *ci = cell.second.get(); + auto tile_name = get_tile_name(ci->bel.tile); + if (!boost::starts_with(tile_name, "CFG_CENTER_")) + continue; + + push(tile_name); + if (ci->type == id_BSCAN_BSCAN) { + push("BSCAN"); + int chain = int_or_default(ci->params, id_JTAG_CHAIN, 1); + if (chain < 1 || 4 < chain) + log_error("Invalid JTAG_CHAIN number of '%d\n'. Allowed values are: 1-4.", chain); + write_bit("JTAG_CHAIN_" + std::to_string(chain)); + pop(); + } + + if (ci->type == id_DCIRESET_DCIRESET) { + write_bit("DCIRESET.ENABLED"); + } + + if (ci->type == id_ICAP_ICAP) { + push("ICAP"); + std::string width = str_or_default(ci->params, id_ICAP_WIDTH, "X32"); + if (width != "X32" && width != "X16" && width != "X8") + log_error("Unknown ICAP_WIDTH of '%s\n'. Allowed values are: X32, X16 and X8.", width.c_str()); + if (width == "X16") write_bit("ICAP_WIDTH_X16"); + if (width == "X8") write_bit("ICAP_WIDTH_X8"); + pop(); + } + + if (ci->type == id_STARTUP_STARTUP) { + std::string prog_usr = str_or_default(ci->params, id_PROG_USR, "FALSE"); + if (prog_usr != "TRUE" && prog_usr != "FALSE") + log_error("Invalid PROG_USR attribute in STARTUPE2 of '%s\n'. Allowed values are: TRUE, FALSE.", prog_usr.c_str()); + write_bit("STARTUP.PROG_USR", prog_usr == "TRUE"); + write_bit("STARTUP.USRCCLKO_CONNECTED", !ctx->net_is_constant(ci->getPort(id_USRCCLKO))); + } + + pop(); + } + } + std::vector used_wires_starting_with(int tile, const std::string &prefix, bool is_source) { std::vector wires; @@ -1618,6 +1662,7 @@ struct FasmBackend { get_invertible_pins(ctx, invertible_pins); write_logic(); + write_cfg(); write_io(); write_routing(); write_bram(); diff --git a/xilinx/pack.cc b/xilinx/pack.cc index 08796ebb7..f679622b3 100644 --- a/xilinx/pack.cc +++ b/xilinx/pack.cc @@ -894,6 +894,7 @@ bool Arch::pack() packer.pack_constants(); packer.pack_iologic(); packer.pack_idelayctrl(); + packer.pack_cfg(); packer.pack_clocking(); packer.pack_muxfs(); packer.pack_carries(); diff --git a/xilinx/pack.h b/xilinx/pack.h index 420c6d32f..59c71f89c 100644 --- a/xilinx/pack.h +++ b/xilinx/pack.h @@ -231,6 +231,9 @@ struct XC7Packer : public XilinxPacker void pack_gbs(); void pack_clocking(); + // CFG + void pack_cfg(); + // BRAM void pack_bram(); diff --git a/xilinx/pack_clocking_xc7.cc b/xilinx/pack_clocking_xc7.cc index 233edcb7d..e02138fa0 100644 --- a/xilinx/pack_clocking_xc7.cc +++ b/xilinx/pack_clocking_xc7.cc @@ -130,6 +130,18 @@ void XC7Packer::pack_gbs() } } +void XC7Packer::pack_cfg() +{ + log_info("Packing cfg...\n"); + dict cfg_rules; + cfg_rules[id_BSCANE2].new_type = id_BSCAN_BSCAN; + cfg_rules[id_DCIRESET].new_type = id_DCIRESET_DCIRESET; + cfg_rules[id_ICAPE2].new_type = id_ICAP_ICAP; + cfg_rules[id_STARTUPE2].new_type = id_STARTUP_STARTUP; + + generic_xform(cfg_rules); +} + void XC7Packer::pack_clocking() { pack_plls(); From 08e231e97e103a00f00d60bd75dbe1cde5e625d1 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Fri, 6 Oct 2023 06:47:33 +0700 Subject: [PATCH 2/4] fix BSCAN type, because of inconsistency in prjxray --- xilinx/constids.inc | 1 - xilinx/fasm.cc | 2 +- xilinx/pack_clocking_xc7.cc | 2 +- 3 files changed, 2 insertions(+), 3 deletions(-) diff --git a/xilinx/constids.inc b/xilinx/constids.inc index 1a1e832b7..47f0582c9 100644 --- a/xilinx/constids.inc +++ b/xilinx/constids.inc @@ -280,7 +280,6 @@ X(BEL) X(BITSLICE_CONTROL_BEL) X(BREG) X(BSCAN) -X(BSCAN_BSCAN) X(BSCANE2) X(BUFG) X(BUFG_BUFG) diff --git a/xilinx/fasm.cc b/xilinx/fasm.cc index ab5396a63..2d35164e9 100644 --- a/xilinx/fasm.cc +++ b/xilinx/fasm.cc @@ -1166,7 +1166,7 @@ struct FasmBackend continue; push(tile_name); - if (ci->type == id_BSCAN_BSCAN) { + if (ci->type == id_BSCAN) { push("BSCAN"); int chain = int_or_default(ci->params, id_JTAG_CHAIN, 1); if (chain < 1 || 4 < chain) diff --git a/xilinx/pack_clocking_xc7.cc b/xilinx/pack_clocking_xc7.cc index e02138fa0..d2fba7feb 100644 --- a/xilinx/pack_clocking_xc7.cc +++ b/xilinx/pack_clocking_xc7.cc @@ -134,7 +134,7 @@ void XC7Packer::pack_cfg() { log_info("Packing cfg...\n"); dict cfg_rules; - cfg_rules[id_BSCANE2].new_type = id_BSCAN_BSCAN; + cfg_rules[id_BSCANE2].new_type = id_BSCAN; cfg_rules[id_DCIRESET].new_type = id_DCIRESET_DCIRESET; cfg_rules[id_ICAPE2].new_type = id_ICAP_ICAP; cfg_rules[id_STARTUPE2].new_type = id_STARTUP_STARTUP; From 4e40899450635780b0f148126c89d8febfa4d6d7 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Tue, 10 Oct 2023 08:31:38 +0700 Subject: [PATCH 3/4] add DNA_PORT, EFUSE_USR, FRAME_ECCE2, USR_ACCESSE2 primitives --- xilinx/constids.inc | 10 ++++++++++ xilinx/pack_clocking_xc7.cc | 12 ++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/xilinx/constids.inc b/xilinx/constids.inc index 47f0582c9..3de7c63d7 100644 --- a/xilinx/constids.inc +++ b/xilinx/constids.inc @@ -367,6 +367,8 @@ X(DIPBDIP0) X(DIPBDIP1) X(DLY_TEST_IN) X(DMONITORCLK) +X(DNA_PORT) +X(DNA_PORT_DNA_PORT) X(DOA_REG) X(DOB_REG) X(DPO) @@ -376,6 +378,8 @@ X(DWE) X(E) X(ECCPIPECE) X(ECCPIPECEL) +X(EFUSE_USR) +X(EFUSE_USR_EFUSE_USR) X(ENARDEN) X(ENBWREN) X(EN_A) @@ -393,6 +397,9 @@ X(FIFO18E1) X(FIFO18E2) X(FIFO36E1) X(FIFO36E2) +X(FRAME_ECCE2) +X(FRAME_ECC) +X(FRAME_ECC_FRAME_ECC) X(G) X(GND) X(GTGREFCLK) @@ -717,6 +724,9 @@ X(TX_RST_DLY) X(T_OUT) X(URAM288_BASE) X(USE_DPORT) +X(USR_ACCESSE2) +X(USR_ACCESS) +X(USR_ACCESS_USR_ACCESS) X(USRCCLKO) X(VCC) X(VREF) diff --git a/xilinx/pack_clocking_xc7.cc b/xilinx/pack_clocking_xc7.cc index d2fba7feb..8b9ef8ceb 100644 --- a/xilinx/pack_clocking_xc7.cc +++ b/xilinx/pack_clocking_xc7.cc @@ -134,10 +134,14 @@ void XC7Packer::pack_cfg() { log_info("Packing cfg...\n"); dict cfg_rules; - cfg_rules[id_BSCANE2].new_type = id_BSCAN; - cfg_rules[id_DCIRESET].new_type = id_DCIRESET_DCIRESET; - cfg_rules[id_ICAPE2].new_type = id_ICAP_ICAP; - cfg_rules[id_STARTUPE2].new_type = id_STARTUP_STARTUP; + cfg_rules[id_BSCANE2].new_type = id_BSCAN; + cfg_rules[id_DCIRESET].new_type = id_DCIRESET_DCIRESET; + cfg_rules[id_DNA_PORT].new_type = id_DNA_PORT_DNA_PORT; + cfg_rules[id_EFUSE_USR].new_type = id_EFUSE_USR_EFUSE_USR; + cfg_rules[id_ICAPE2].new_type = id_ICAP_ICAP; + cfg_rules[id_FRAME_ECCE2].new_type = id_FRAME_ECC_FRAME_ECC; + cfg_rules[id_STARTUPE2].new_type = id_STARTUP_STARTUP; + cfg_rules[id_USR_ACCESSE2].new_type = id_USR_ACCESS_USR_ACCESS; generic_xform(cfg_rules); } From 11b9216df7ca7558e847b68a4cf6b8a3ffb8bdcf Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Thu, 12 Oct 2023 10:27:52 +0700 Subject: [PATCH 4/4] README.md: update supported primitives --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index dcb0db6d6..edd0e0901 100644 --- a/README.md +++ b/README.md @@ -66,7 +66,7 @@ on [arXiv](https://arxiv.org/abs/1903.10407). - Currently supported: - xc7 and xcup: LUTs (including fractured), FFs, DRAM (only RAM64X1D), carry (XORCY and MUXCY or CARRY4), SRL16E and SRLC32E (no cascading), BRAM and IO - xcup: OSERDESE3, ISERDESE3, IDDRE1, ODDRE1, IDELAYE3, ODELAYE3, IDELAYCTRL, BUFGCTRL, BUFG, BUFGCE, BUFG_PS, PLLE4_ADV, PLLE4_BASIC, MMCME4_ADV, MMCME4_BASIC, URAM288E, DSP48E2 (no cascading) - - xc7: OSERDESE2, ISERDESE2, IDDR, ODDR, IDELAYE2, ODELAYE2, IDELAYCTRL, BUFGCTRL, BUFG, PLLE2_BASIC, PLLE2_ADV, DSP48E1 (cascading works) + - xc7: OSERDESE2, ISERDESE2, IDDR, ODDR, IDELAYE2, ODELAYE2, IDELAYCTRL, BUFGCTRL, BUFG, PLLE2_BASIC, PLLE2_ADV, DSP48E1 (cascading works), STARTUPE2, BSCANE2, ICAPE2, DCIRESET, DNA_PORT, EFUSE_USR, FRAME_ECCE2, USR_ACCESSE2 - Bels, tile wires and pips are deduplicated but nodes (connections between tile wires) are not. This means that databases for larger devices will be several gigabytes in size (but significantly smaller than a fully flat database).