Placer does not terminate for example design

[hansfbaier]

This example SoC build well with f4pga and Vivado, but does not terminate with default settings:
https://github.com/chili-chips-ba/openXC7-TetriSaraj.git
29a8501669b167c55efc5da87a8ae7402271d986
When I use --placer-heap-cell-placement-timeout 2048 then it terminates with the error message

Info: Running main analytical placer, max placement attempts per cell = 493396.
ERROR: Unable to find legal placement for cell 'at.ram.ram.1.24.0/DPR0' after 493397 attempts, check constraints and utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of attempts.
0 warnings, 1 error

This looks like something is wrong with the RAM placer constraints. Could that be a casualty of
#56 ?

Update: I tried to build without -nobram in yosys, but I get a similar result:

Info: Placed 149 cells based on constraints.
Info: Creating initial analytic placement for 8609 cells, random placement wirelen = 1904059.
Info:     at initial placer iter 0, wirelen = 13918
Info:     at initial placer iter 1, wirelen = 10766
Info:     at initial placer iter 2, wirelen = 10250
Info:     at initial placer iter 3, wirelen = 10344
Info: Running main analytical placer, max placement attempts per cell = 282611.
ERROR: Unable to find legal placement for cell 'at.ram.ram.1.31.0/DPR0' after 282612 attempts, check constraints and utilisation. Use `--placer-heap-cell-placement-timeout` to change the number of attempts.
0 warnings, 1 error

[hansfbaier]

How could I debug this and get to the bottom of this issue?

[hansfbaier]

@gatecat Could it be that if the placer runs out of SLICEMs that it just loops endlessly?
That is what it looks like. There is a lot of LUT ram in the design and after some time placing them, it does not seem to get any valid SLICEM tiles anymore.
Is there somewhere kept track of how many SLICEM's have been allocated?
I guess it is not possible to know that before placing?

[hansfbaier]

Anyway, the authors of the demo project said they could successfully place and route the project with both vivado and f4pga/VPR, so in principle the resources should be available.