Constraints issue using generated chipdb file

[Pocketkid2]

I think I've encountered a bug that affects the pin mapping for the Basys3 board (part name xc7a35tcpg236-1). I've got a program that maps the 16 switches to a seven segment display but the behavior of the circuit when generated through NextPNR is incorrect compared to the same design run through Vivado and VPR.

My constraints file contains the following:

set_property -dict { PACKAGE_PIN V17   IOSTANDARD LVCMOS33 } [get_ports sw[0]]
set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports sw[1]]
set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports sw[2]]
set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports sw[3]]
set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports sw[4]]
set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports sw[5]]

sw[2] and sw[3] correspond to the third and fourth switches from the left, respectively. The problem is that their pins seem to be swapped in the final design, so that the behavior of sw[2] when compiled through NextPNR-xilinx matches the behavior of sw[3] when compiled through Vivado and VPR, and vice versa for those same two. I think this could be a problem with the .bba or .bin chip database file created from the NextPNR-xilinx project, or maybe a bug with NextPNR itself.

The commands I'm using to generate the db files:

pypy3 xilinx/python/bbaexport.py --device xc7a35tcpg236-1 --bba xilinx/xc7a35tcpg236-1.bba --xray $(prjxray-config)/artix7
./bbasm --l xilinx/xc7a35tcpg236-1.bba xilinx/xc7a35tcpg236-1.bin

[Xiretza]

The same issue occurs for xc7a35tcsg324-1 with pins U12 and V12. On the Arty-A7 board, these should correspond to PMOD_C[0] and PMOD_C[1], but nextpnr-xilinx reverses them. All other PMOD pins are fine.