Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

nextpnr-xilinx crash when using 1.8V input pin on a Kintex 7 325T fpga #36

Open
infphyny opened this issue Apr 9, 2022 · 0 comments
Open

Comments

@infphyny
Copy link

infphyny commented Apr 9, 2022

I have made a simple blinky example for a xc7k325tffg676-1 fpga with a reset input on a pin with constraint IOSTANDARD LVCMOS18 . The reset input is located at pin AF9 . A repro can be provided upon request.
If I remove the reset pin, I can generate bitstream and program successfully fpga.

The output of nextpnr-xilinx is:

nextpnr-xilinx -r --chipdb /usr/local/share/nextpnr/xilinx-chipdb/xc7k325tffg676-1.bin --xdc data/constraints.xdc --json blinky.json --write blinky_routed.json --fasm blinky.fasm --freq 50
Info: Packing constants..
Info: Inserting IO buffers..
Info:     IO port 'i_clock_50MHz' driven by IBUF '$iopadmap$Top.i_clock_50MHz'
Info:     IO port 'i_reset_n' driven by IBUF '$iopadmap$Top.i_reset_n'
Info:     IO port 'o_leds[0]' driven by OBUF '$iopadmap$Top.o_leds'
Info:     IO port 'o_leds[1]' driven by OBUF '$iopadmap$Top.o_leds_1'
Info:     IO port 'o_leds[2]' driven by OBUF '$iopadmap$Top.o_leds_2'
Info:     Constraining 'i_clock_50MHz' to site 'IOB_X0Y126'
Info:     Constraining 'i_reset_n' to site 'IOB_X1Y51'
Info:     Constraining 'o_leds[0]' to site 'IOB_X0Y114'
Info:     Constraining 'o_leds[1]' to site 'IOB_X0Y113'
Info:     Constraining 'o_leds[2]' to site 'IOB_X0Y231'
Info: Generating input buffer for '$iopadmap$Top.i_clock_50MHz'
Info: Generating input buffer for '$iopadmap$Top.i_reset_n'
terminate called after throwing an instance of 'nextpnr_xilinx::assertion_failure'
  what():  Assertion failure: s != -1 (/nextpnr-xilinx/xilinx/arch.h:1602)
make: *** [Makefile:21: blinky.fasm] Abandon (core dump créé)

The problem seem that nexpnr-xilinx automatically add "/IOB33/PAD" to all site and don't seem to check for io voltage.
Inside pack_io_xc7.cc XC7Packer::pack_io() function

pad->attrs[ctx->id("BEL")] = std::string(site + "/IOB33/PAD");

I think for pin AF9 or all other pin with 1.8V logic level there should be code like this :

pad->attrs[ctx->id("BEL")] = std::string(site + "/IOB18/PAD");

I have added code in file pack_io_xc7.cc to print additional information to show the site and pad attribute information. here is the output for pin AF9 with 1.8V io :

pack_io_xc7.cc::pack_io LOC: AF9
Pin name: AF9
pack_io_xc7.cc::pack_io SITE: IOB_X1Y51
Info:     Constraining 'i_reset_n' to site 'IOB_X1Y51'
pack_io_xc7.cc::pack_io pad->attrs[ctx->id("BEL")] : IOB_X1Y51/IOB33/PAD

Then in the file prjxray-db/kintex7/xc7k325t/tilegrid.json For pin AF9 at site IOB_X1Y51 is defined as

tilegrid.json:1331353:            "IOB_X1Y51": "IO_L24N_T3_33",
tilegrid.json:1331358:            "IOB_X1Y51": "IOB18S",

Here are the other 3.3V pins for comparison that nextpnr-xilinx place successfully.

Pin i_clock_50MHz at site IOB_X0Y126:

pack_io_xc7.cc::pack_io LOC: F22
Pin name: F22
pack_io_xc7.cc::pack_io SITE: IOB_X0Y126
Info:     Constraining 'i_clock_50MHz' to site 'IOB_X0Y126'
pack_io_xc7.cc::pack_io pad->attrs[ctx->id("BEL")] : IOB_X0Y126/IOB33/PAD

Tile grid definition:

tilegrid.json:1235714:            "IOB_X0Y126": "IO_L12P_T1_MRCC_14"
tilegrid.json:1235719:            "IOB_X0Y126": "IOB33M"


Pin o_leds[0] at site IOB_X0Y114

pack_io_xc7.cc::pack_io LOC: J26
Pin name: J26
pack_io_xc7.cc::pack_io SITE: IOB_X0Y114
Info:     Constraining 'o_leds[0]' to site 'IOB_X0Y114'
pack_io_xc7.cc::pack_io pad->attrs[ctx->id("BEL")] : IOB_X0Y114/IOB33/PAD

Tilegrid definition:

tilegrid.json:1235576:            "IOB_X0Y114": "IO_L18P_T2_A12_D28_14"
tilegrid.json:1235581:            "IOB_X0Y114": "IOB33M"


Pin o_leds[1] at site IOB_X0Y113

pack_io_xc7.cc::pack_io LOC: H26
Pin name: H26
pack_io_xc7.cc::pack_io SITE: IOB_X0Y113
Info:     Constraining 'o_leds[1]' to site 'IOB_X0Y113'
pack_io_xc7.cc::pack_io pad->attrs[ctx->id("BEL")] : IOB_X0Y113/IOB33/PAD

Tilegrid definition:

tilegrid.json:1235575:            "IOB_X0Y113": "IO_L18N_T2_A11_D27_14",
tilegrid.json:1235580:            "IOB_X0Y113": "IOB33S",


Pin o_leds[2] at site IOB_X0Y231

pack_io_xc7.cc::pack_io LOC: A8
Pin name: A8
pack_io_xc7.cc::pack_io SITE: IOB_X0Y231
Info:     Constraining 'o_leds[2]' to site 'IOB_X0Y231'
pack_io_xc7.cc::pack_io pad->attrs[ctx->id("BEL")] : IOB_X0Y231/IOB33/PAD

Tilegrid definition

tilegrid.json:1236886:            "IOB_X0Y231": "IO_L9N_T1_DQS_16",
tilegrid.json:1236891:            "IOB_X0Y231": "IOB33S",

Thanks.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant