Adding external constraints to class object #205
Replies: 3 comments 5 replies
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@eliran-arbili I think your example should work, but I think the constraints list in the base_rand_class and ptr within user_constraints_class are causing recursion issues. I believe when pyvsc walks down the rand variables it keeps self-referencing via the ptr. I tried debugging in vscode and even trying to look at the object causes it to crash... Also, wrapping up your examples in code blocks would be helpful. The double underscores and indentations for python were lost in the conversion. You can add I've re-written your example into something that doesn't self-reference the constraints list, but hopefully is close to what you were accomplishing in SV! @vsc.randobj
class base_constraints_class(object):
pass
@vsc.randobj
class base_rand_class(object):
def __init__(self, name):
self.name = name
self.user = vsc.rand_attr(user_rand_class(name))
self.constraints = vsc.rand_list_t(base_constraints_class())
def add_constraints(self, c):
self.constraints.append(c)
@vsc.randobj
class user_constraints_class_a(base_constraints_class):
def __init__(self, ptr):
self.ptr = vsc.rand_attr(ptr)
@vsc.constraint
def my_ptr_c(self):
self.ptr.a == 8
@vsc.randobj
class user_constraints_class_b(base_constraints_class):
def __init__(self, ptr):
self.ptr = vsc.rand_attr(ptr)
@vsc.constraint
def my_ptr_c(self):
self.ptr.b == 1999
@vsc.randobj
class user_rand_class(object):
def __init__(self, name):
self.name = name
self.a = vsc.rand_bit_t(16)
self.b = vsc.rand_bit_t(16)
@vsc.constraint
def ab_c(self):
self.a in vsc.rangelist(vsc.rng(1,1000))
self.b in vsc.rangelist(vsc.rng(1000,2000))
def print_fields(self):
print(f"{self.name}: a={self.a}, b={self.b}")
def main(argv):
usr1 = base_rand_class("user_1")
usr1.add_constraints(user_constraints_class_a(usr1.user))
usr1.add_constraints(user_constraints_class_b(usr1.user))
usr1.randomize(debug=0)
print("--------------------\n")
usr1.user.print_fields()
if __name__ == "__main__":
main(sys.argv[1:])
--------------------
user_1: a=8, b=1999 |
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Hi @eliran-arbili, @alwilson, I'll continue looking into this, since I do expect this case to work (ie there's nothing inherently broken about the pattern). -Matthew |
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Hi @eliran-arbili, the core issue is that there's a recursive relationship between the two classes and PyVSC wasn't originally designed to support this. I had thought that it wouldn't be realistic to support this using the existing PyVSC implementation, but after revisiting, I believe it can be done. I've released version 0.8.9 that allows your testcase to run. I haven't attempted to validate that it is behaving as you expect -- it may not. It's probably also worth revisiting what you "really" want here. The SystemVerilog implementation of dynamically-layered constraints is necessitated by the SystemVerilog language features. It's quite possible that there is a easier/simpler/lighter-weight approach enabled by Python. So, I would be interested in understanding the your usecase here! |
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Hi,
I'm starting to play with pyvsc and I'm trying to convert some SV code we have to python.
Here is a simplified example of the code I'm trying to convert:
**Output with VCS:
usr1.a=8, usr1.b=1999, usr1.d=2**
I tried to implement same idea with pyvsc but without success so far.
Any idea what is wrong?:
Failing on:
((self.is_declared_rand and self.rand_mode) or level==0))
RecursionError: maximum recursion depth exceeded
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