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Add test to show accessing 'width' property
Signed-off-by: Matthew Ballance <[email protected]>
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2 files changed

+54
-24
lines changed

2 files changed

+54
-24
lines changed

ivpm.yaml

+26-24
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,29 @@
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package:
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name: pyvsc
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version: None
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name: pyvsc
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dep-sets:
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- name: default
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deps:
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- name: pyboolector
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type: python
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src: pypi
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- name: toposort
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src: pypi
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- name: pyucis
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src: pypi
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dev-deps:
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- name: mkdv
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url: https://github.com/fvutils/mkdv.git
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- name: pyboolector
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src: pypi
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- name: pytest
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src: pypi
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- name: pytest-cov
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src: pypi
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- name: toposort
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src: pypi
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- name: pyucis
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url: https://github.com/fvutils/pyucis.git
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- name: riscv-dv
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url: https://github.com/google/riscv-dv.git
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- name: pyboolector
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src: pypi
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- name: toposort
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src: pypi
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- name: pyucis
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src: pypi
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- name: default-dev
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deps:
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# - name: mkdv
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# url: https://github.com/fvutils/mkdv.git
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- name: pyboolector
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src: pypi
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- name: pytest
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src: pypi
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- name: pytest-cov
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src: pypi
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- name: toposort
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src: pypi
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- name: pyucis
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url: https://github.com/fvutils/pyucis.git
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- name: riscv-dv
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url: https://github.com/google/riscv-dv.git
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ve/unit/test_field_standalone.py

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Original file line numberDiff line numberDiff line change
@@ -205,3 +205,31 @@ def test_bit_partselect(self):
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self.assertEqual(field.get_val()[0], 1)
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self.assertEqual(field.get_val()[8], 0)
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def test_width(self):
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import vsc
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my_bit_field = vsc.rand_bit_t(16) # 16-bit wide
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width = my_bit_field.width
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print(f"The width of the bit field is: {width} bits")
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@vsc.randobj
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class my_s(object):
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def __init__(self):
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self.x = vsc.rand_bit_t(16)
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@vsc.constraint
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def ab_c(self):
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self.x in vsc.rangelist(1, 2, 4, 8)
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def print_width(self):
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with vsc.raw_mode():
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width=self.x.width
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print(f'{width}')
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obj=my_s()
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for i in range(2):
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obj.randomize()
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obj.print_width()
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