ci(pre-commit): Apply automatic fixes

Author: pre-commit-ci-lite[bot]

cores/esp32/HardwareSerial.cpp

@@ -360,7 +360,7 @@ void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, in
           txPin = _txPin < 0 ? (int8_t)TX1 : _txPin;
         }
         break;
-#endif // UART_NUM_1
+#endif  // UART_NUM_1
 #if SOC_UART_HP_NUM > 2
       case UART_NUM_2:
         if (rxPin < 0 && txPin < 0) {
@@ -386,7 +386,7 @@ void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, in
 #endif
         }
         break;
-#endif // UART_NUM_3
+#endif  // UART_NUM_3
 #if SOC_UART_HP_NUM > 4
       case UART_NUM_4:
         if (rxPin < 0 && txPin < 0) {
@@ -405,14 +405,14 @@ void HardwareSerial::begin(unsigned long baud, uint32_t config, int8_t rxPin, in
         if (rxPin < 0 && txPin < 0) {
           // do not change RX0_LP/TX0_LP if it has already been set before
 #ifdef LP_RX0
-          rxPin = _rxPin < 0 ? (int8_t)LP_RX0 : _rxPin;   
+          rxPin = _rxPin < 0 ? (int8_t)LP_RX0 : _rxPin;
 #endif
 #ifdef LP_TX0
           txPin = _txPin < 0 ? (int8_t)LP_TX0 : _txPin;
 #endif
         }
         break;
-#endif // LP_UART_NUM_0
+#endif  // LP_UART_NUM_0
     }
   }
 
@@ -628,7 +628,7 @@ size_t HardwareSerial::setRxBufferSize(size_t new_size) {
     return 0;
   }
   uint8_t FIFOLen = UART_HW_FIFO_LEN(_uart_nr);
-  // Valid value is higher than the FIFO length 
+  // Valid value is higher than the FIFO length
   if (new_size <= FIFOLen) {
     new_size = FIFOLen + 1;
     log_w("RX Buffer set to minimum value: %d.", new_size);
@@ -648,7 +648,7 @@ size_t HardwareSerial::setTxBufferSize(size_t new_size) {
   }
   uint8_t FIFOLen = UART_HW_FIFO_LEN(_uart_nr);
   // Valid values are zero or higher than the FIFO length
-  if (new_size > 0  && new_size <= FIFOLen) {
+  if (new_size > 0 && new_size <= FIFOLen) {
     new_size = FIFOLen + 1;
     log_w("TX Buffer set to minimum value: %d.", new_size);
   }

cores/esp32/HardwareSerial.h

@@ -214,11 +214,11 @@ typedef enum {
 
 #if SOC_UART_LP_NUM >= 1
 #ifndef LP_RX0
-#define LP_RX0 (gpio_num_t)LP_U0RXD_GPIO_NUM
+#define LP_RX0 (gpio_num_t) LP_U0RXD_GPIO_NUM
 #endif
 
 #ifndef LP_TX0
-#define LP_TX0 (gpio_num_t)LP_U0TXD_GPIO_NUM
+#define LP_TX0 (gpio_num_t) LP_U0TXD_GPIO_NUM
 #endif
 #endif /* SOC_UART_LP_NUM >= 1 */
 

cores/esp32/esp32-hal-uart.c

@@ -67,7 +67,7 @@ struct uart_struct_t {
 
 static uart_t _uart_bus_array[] = {
   {0, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
- #if SOC_UART_NUM > 1
+#if SOC_UART_NUM > 1
   {1, false, 0, NULL, -1, -1, -1, -1, 0, 0, 0, 0, false, 0},
 #endif
 #if SOC_UART_NUM > 2
@@ -117,8 +117,7 @@ static uart_t _uart_bus_array[] = {
 
 #if SOC_UART_LP_NUM >= 1
 // LP UART enable pins routine
-static bool lp_uart_config_io(uint8_t uart_num, int8_t pin, rtc_gpio_mode_t direction, uint32_t idx)
-{
+static bool lp_uart_config_io(uint8_t uart_num, int8_t pin, rtc_gpio_mode_t direction, uint32_t idx) {
   /* Skip configuration if the LP_IO is -1 */
   if (pin < 0) {
     return true;
@@ -138,21 +137,21 @@ static bool lp_uart_config_io(uint8_t uart_num, int8_t pin, rtc_gpio_mode_t dire
 
   // Connect pins
   const uart_periph_sig_t *upin = &uart_periph_signal[uart_num].pins[idx];
-#if !SOC_LP_GPIO_MATRIX_SUPPORTED // ESP32-C6/C61/C5
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED  // ESP32-C6/C61/C5
   // When LP_IO Matrix is not support, LP_IO Mux must be connected to the pins
   if (rtc_gpio_iomux_func_sel(pin, upin->iomux_func) != ESP_OK) {
     log_e("Failed to set LP_IO pin %d into Mux function", pin);
     return false;
   }
-#else // So far, only ESP32-P4
+#else   // So far, only ESP32-P4
   // If the configured pin is the default LP_IO Mux pin for LP UART, then set the LP_IO MUX function
   if (upin->default_gpio == pin) {
     if (rtc_gpio_iomux_func_sel(pin, upin->iomux_func) != ESP_OK) {
       log_e("Failed to set LP_IO pin %d into Mux function", pin);
       return false;
     }
   } else {
-    // Otherwise, set the LP_IO Matrix and select FUNC1 
+    // Otherwise, set the LP_IO Matrix and select FUNC1
     if (rtc_gpio_iomux_func_sel(pin, 1) != ESP_OK) {
       log_e("Failed to set LP_IO pin %d into Mux function GPIO", pin);
       return false;
@@ -169,43 +168,43 @@ static bool lp_uart_config_io(uint8_t uart_num, int8_t pin, rtc_gpio_mode_t dire
       return false;
     }
   }
-#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
+#endif  // SOC_LP_GPIO_MATRIX_SUPPORTED
 
   return true;
 }
 
 // When LP UART needs the RTC IO MUX to set the pin, it will always have fixed pins for RX, TX, CTS and RTS
 static bool lpuartCheckPins(int8_t rxPin, int8_t txPin, int8_t ctsPin, int8_t rtsPin, uint8_t uart_nr) {
-  // check if LP UART is being used and if the pins are valid
-  #if !SOC_LP_GPIO_MATRIX_SUPPORTED // ESP32-C6/C61/C5
-    uint16_t lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RX_PIN_IDX].default_gpio;
-    if (uart_nr >= SOC_UART_HP_NUM) { // it is a LP UART NUM
-      if (rxPin > 0 && rxPin != lp_uart_fixed_pin) {
-        log_e("UART%d LP UART requires RX pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
-        return false;
-      }
-      lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_TX_PIN_IDX].default_gpio;
-      if (txPin > 0 && txPin != lp_uart_fixed_pin) {
-        log_e("UART%d LP UART requires TX pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
-        return false;
-      }
-      lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_CTS_PIN_IDX].default_gpio;
-      if (ctsPin > 0 && ctsPin != lp_uart_fixed_pin) {
-        log_e("UART%d LP UART requires CTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
-        return false;
-      }
-      lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RTS_PIN_IDX].default_gpio;
-      if (rtsPin > 0 && rtsPin != lp_uart_fixed_pin) {
-        log_e("UART%d LP UART requires RTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
-        return false;
-      }
+// check if LP UART is being used and if the pins are valid
+#if !SOC_LP_GPIO_MATRIX_SUPPORTED  // ESP32-C6/C61/C5
+  uint16_t lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RX_PIN_IDX].default_gpio;
+  if (uart_nr >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
+    if (rxPin > 0 && rxPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires RX pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
+    }
+    lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_TX_PIN_IDX].default_gpio;
+    if (txPin > 0 && txPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires TX pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
+    }
+    lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_CTS_PIN_IDX].default_gpio;
+    if (ctsPin > 0 && ctsPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires CTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
+    }
+    lp_uart_fixed_pin = uart_periph_signal[uart_nr].pins[SOC_UART_RTS_PIN_IDX].default_gpio;
+    if (rtsPin > 0 && rtsPin != lp_uart_fixed_pin) {
+      log_e("UART%d LP UART requires RTS pin to be set to %d.", uart_nr, lp_uart_fixed_pin);
+      return false;
+    }
   }
   return true;
-#else // ESP32-P4 can set any pin for LP UART
+#else   // ESP32-P4 can set any pin for LP UART
   return true;
-#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
+#endif  // SOC_LP_GPIO_MATRIX_SUPPORTED
 }
-#endif // SOC_UART_LP_NUM >= 1
+#endif  // SOC_UART_LP_NUM >= 1
 
 // Negative Pin Number will keep it unmodified, thus this function can detach individual pins
 // This function will also unset the pins in the Peripheral Manager and set the pin to -1 after detaching
@@ -305,7 +304,7 @@ static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t
   uart_t *uart = &_uart_bus_array[uart_num];
   //log_v("attaching UART%d pins: prev,new RX(%d,%d) TX(%d,%d) CTS(%d,%d) RTS(%d,%d)", uart_num,
   //        uart->_rxPin, rxPin, uart->_txPin, txPin, uart->_ctsPin, ctsPin, uart->_rtsPin, rtsPin); vTaskDelay(10);
-  
+
   // IDF uart_set_pin() checks if the pin is used within LP UART and if it is a valid RTC IO pin
   // No need for Arduino Layer to check it again
   bool retCode = true;
@@ -317,7 +316,7 @@ static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t
     // connect RX Pad
     bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, rxPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
 #if SOC_UART_LP_NUM >= 1
-    if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
       ret &= lp_uart_config_io(uart->num, rxPin, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_RX_PIN_IDX);
     }
 #endif
@@ -340,7 +339,7 @@ static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t
     // connect TX Pad
     bool ret = ESP_OK == uart_set_pin(uart->num, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
 #if SOC_UART_LP_NUM >= 1
-    if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
       ret &= lp_uart_config_io(uart->num, txPin, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_TX_PIN_IDX);
     }
 #endif
@@ -363,7 +362,7 @@ static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t
     // connect CTS Pad
     bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, ctsPin);
 #if SOC_UART_LP_NUM >= 1
-    if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
       ret &= lp_uart_config_io(uart->num, ctsPin, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_CTS_PIN_IDX);
     }
 #endif
@@ -386,7 +385,7 @@ static bool _uartAttachPins(uint8_t uart_num, int8_t rxPin, int8_t txPin, int8_t
     // connect RTS Pad
     bool ret = ESP_OK == uart_set_pin(uart->num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, rtsPin, UART_PIN_NO_CHANGE);
 #if SOC_UART_LP_NUM >= 1
-    if (ret && uart_num >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+    if (ret && uart_num >= SOC_UART_HP_NUM) {  // it is a LP UART NUM
       ret &= lp_uart_config_io(uart->num, rtsPin, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_RTS_PIN_IDX);
     }
 #endif
@@ -551,7 +550,7 @@ uart_t *uartBegin(
   }
   uart_t *uart = &_uart_bus_array[uart_nr];
   log_v("UART%d baud(%ld) Mode(%x) rxPin(%d) txPin(%d)", uart_nr, baudrate, config, rxPin, txPin);
-  
+
 #if SOC_UART_LP_NUM >= 1
   // check if LP UART is being used and if the pins are valid
   if (!lpuartCheckPins(rxPin, txPin, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, uart_nr)) {
@@ -664,14 +663,17 @@ uart_t *uartBegin(
   uart_config.stop_bits = (config & 0x30) >> 4;
   uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
   uart_config.rx_flow_ctrl_thresh = rxfifo_full_thrhd >= UART_HW_FIFO_LEN(uart_nr) ? UART_HW_FIFO_LEN(uart_nr) - 6 : rxfifo_full_thrhd;
-  log_v("UART%d RX FIFO full threshold set to %d (value requested: %d || FIFO Max = %d)", uart_nr, uart_config.rx_flow_ctrl_thresh, rxfifo_full_thrhd, UART_HW_FIFO_LEN(uart_nr));
-  rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh; // makes sure that it will be set correctly in the struct
+  log_v(
+    "UART%d RX FIFO full threshold set to %d (value requested: %d || FIFO Max = %d)", uart_nr, uart_config.rx_flow_ctrl_thresh, rxfifo_full_thrhd,
+    UART_HW_FIFO_LEN(uart_nr)
+  );
+  rxfifo_full_thrhd = uart_config.rx_flow_ctrl_thresh;  // makes sure that it will be set correctly in the struct
   uart_config.baud_rate = baudrate;
 #if SOC_UART_LP_NUM >= 1
-  if (uart_nr >= SOC_UART_HP_NUM) { // it is a LP UART NUM
+  if (uart_nr >= SOC_UART_HP_NUM) {                    // it is a LP UART NUM
     uart_config.lp_source_clk = LP_UART_SCLK_DEFAULT;  // use default LP clock
     log_v("Setting UART%d to use LP clock", uart_nr);
-  } else 
+  } else
 #endif
   {
     // there is an issue when returning from light sleep with the C6 and H2: the uart baud rate is not restored
@@ -982,11 +984,11 @@ void uartSetBaudRate(uart_t *uart, uint32_t baud_rate) {
     newClkSrc = LP_UART_SCLK_DEFAULT;  // use default LP clock
   }
 #endif
-// ESP32-P4 demands an atomic operation for setting the clock source
-HP_UART_SRC_CLK_ATOMIC() {
-  uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
-}
-#else // ESP32, ESP32-S2
+  // ESP32-P4 demands an atomic operation for setting the clock source
+  HP_UART_SRC_CLK_ATOMIC() {
+    uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
+  }
+#else  // ESP32, ESP32-S2
   soc_module_clk_t newClkSrc = baud_rate <= REF_TICK_BAUDRATE_LIMIT ? SOC_MOD_CLK_REF_TICK : SOC_MOD_CLK_APB;
   uart_ll_set_sclk(UART_LL_GET_HW(uart->num), newClkSrc);
 #endif