BREAKING - Use IRAM_ATTR in place of ICACHE_RAM_ATTR (#7921)

Update the core to use the define that the ESP32 uses, IRAM_ATTR, for
placing code in DRAM.

Author: earlephilhower

cores/esp8266/FunctionalInterrupt.cpp

@@ -10,7 +10,7 @@ typedef void (*voidFuncPtrArg)(void*);
 extern "C" void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtr userFunc, void*fp, int mode, bool functional);
 
 
-void ICACHE_RAM_ATTR interruptFunctional(void* arg)
+void IRAM_ATTR interruptFunctional(void* arg)
 {
     ArgStructure* localArg = (ArgStructure*)arg;
 	if (localArg->functionInfo->reqScheduledFunction)

cores/esp8266/cbuf.cpp

@@ -67,7 +67,7 @@ size_t cbuf::resize(size_t newSize) {
     return _size;
 }
 
-size_t ICACHE_RAM_ATTR cbuf::available() const {
+size_t IRAM_ATTR cbuf::available() const {
     if(_end >= _begin) {
         return _end - _begin;
     }
@@ -108,7 +108,7 @@ size_t cbuf::peek(char *dst, size_t size) {
     return size_read;
 }
 
-int ICACHE_RAM_ATTR cbuf::read() {
+int IRAM_ATTR cbuf::read() {
     if(empty())
         return -1;
 
@@ -133,7 +133,7 @@ size_t cbuf::read(char* dst, size_t size) {
     return size_read;
 }
 
-size_t ICACHE_RAM_ATTR cbuf::write(char c) {
+size_t IRAM_ATTR cbuf::write(char c) {
     if(full())
         return 0;
 

cores/esp8266/cont_util.cpp

@@ -42,7 +42,7 @@ void cont_init(cont_t* cont) {
     }
 }
 
-int ICACHE_RAM_ATTR cont_check(cont_t* cont) {
+int IRAM_ATTR cont_check(cont_t* cont) {
     if(cont->stack_guard1 != CONT_STACKGUARD || cont->stack_guard2 != CONT_STACKGUARD) return 1;
 
     return 0;
@@ -62,7 +62,7 @@ int cont_get_free_stack(cont_t* cont) {
     return freeWords * 4;
 }
 
-bool ICACHE_RAM_ATTR cont_can_yield(cont_t* cont) {
+bool IRAM_ATTR cont_can_yield(cont_t* cont) {
     return !ETS_INTR_WITHINISR() &&
            cont->pc_ret != 0 && cont->pc_yield == 0;
 }

cores/esp8266/core_esp8266_i2s.cpp

@@ -61,7 +61,7 @@ typedef struct i2s_state {
   uint32_t *       curr_slc_buf; // Current buffer for writing
   uint32_t         curr_slc_buf_pos; // Position in the current buffer
   void             (*callback) (void);
-  // Callback function should be defined as 'void ICACHE_RAM_ATTR function_name()',
+  // Callback function should be defined as 'void IRAM_ATTR function_name()',
   // and be placed in IRAM for faster execution. Avoid long computational tasks in this
   // function, use it to set flags and process later.
   bool             driveClocks;
@@ -139,7 +139,7 @@ uint16_t i2s_rx_available(){
 }
 
 // Pop the top off of the queue and return it
-static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
+static uint32_t * IRAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
   uint8_t i;
   uint32_t *item = ch->slc_queue[0];
   ch->slc_queue_len--;
@@ -150,7 +150,7 @@ static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
 }
 
 // Append an item to the end of the queue from receive
-static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
+static void IRAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
   // Shift everything up, except for the one corresponding to this item
   for (int i=0, dest=0; i < ch->slc_queue_len; i++) {
     if (ch->slc_queue[i] != item) {
@@ -164,7 +164,7 @@ static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t
   }
 }
 
-static void ICACHE_RAM_ATTR i2s_slc_isr(void) {
+static void IRAM_ATTR i2s_slc_isr(void) {
   ETS_SLC_INTR_DISABLE();
   uint32_t slc_intr_status = SLCIS;
   SLCIC = 0xFFFFFFFF;

cores/esp8266/core_esp8266_phy.cpp

@@ -300,10 +300,10 @@ static const uint8_t ICACHE_FLASH_ATTR phy_init_data[128] =
 static bool spoof_init_data = false;
 
 extern int __real_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
-extern int ICACHE_RAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
+extern int IRAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
 extern int __get_adc_mode();
 
-extern int ICACHE_RAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size)
+extern int IRAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size)
 {
     if (!spoof_init_data || size != 128) {
         return __real_spi_flash_read(addr, dst, size);
@@ -354,6 +354,6 @@ void user_rf_pre_init()
 }
 
 
-void ICACHE_RAM_ATTR user_spi_flash_dio_to_qio_pre_init() {}
+void IRAM_ATTR user_spi_flash_dio_to_qio_pre_init() {}
 
 };

cores/esp8266/core_esp8266_si2c.cpp

@@ -103,23 +103,23 @@ class Twi
     ETSTimer timer;
 
     // Event/IRQ callbacks, so they can't use "this" and need to be static
-    static void ICACHE_RAM_ATTR onSclChange(void);
-    static void ICACHE_RAM_ATTR onSdaChange(void);
+    static void IRAM_ATTR onSclChange(void);
+    static void IRAM_ATTR onSdaChange(void);
     static void eventTask(ETSEvent *e);
-    static void ICACHE_RAM_ATTR onTimer(void *unused);
+    static void IRAM_ATTR onTimer(void *unused);
 
     // Allow not linking in the slave code if there is no call to setAddress
     bool _slaveEnabled = false;
 
     // Internal use functions
-    void ICACHE_RAM_ATTR busywait(unsigned int v);
+    void IRAM_ATTR busywait(unsigned int v);
     bool write_start(void);
     bool write_stop(void);
     bool write_bit(bool bit);
     bool read_bit(void);
     bool write_byte(unsigned char byte);
     unsigned char read_byte(bool nack);
-    void ICACHE_RAM_ATTR onTwipEvent(uint8_t status);
+    void IRAM_ATTR onTwipEvent(uint8_t status);
 
     // Handle the case where a slave needs to stretch the clock with a time-limited busy wait
     inline void WAIT_CLOCK_STRETCH()
@@ -149,8 +149,8 @@ class Twi
     uint8_t transmit(const uint8_t* data, uint8_t length);
     void attachSlaveRxEvent(void (*function)(uint8_t*, size_t));
     void attachSlaveTxEvent(void (*function)(void));
-    void ICACHE_RAM_ATTR reply(uint8_t ack);
-    void ICACHE_RAM_ATTR releaseBus(void);
+    void IRAM_ATTR reply(uint8_t ack);
+    void IRAM_ATTR releaseBus(void);
     void enableSlave();
 };
 
@@ -229,7 +229,7 @@ void Twi::enableSlave()
     }
 }
 
-void ICACHE_RAM_ATTR Twi::busywait(unsigned int v)
+void IRAM_ATTR Twi::busywait(unsigned int v)
 {
     unsigned int i;
     for (i = 0; i < v; i++)  // loop time is 5 machine cycles: 31.25ns @ 160MHz, 62.5ns @ 80MHz
@@ -472,9 +472,9 @@ void Twi::attachSlaveTxEvent(void (*function)(void))
 }
 
 // DO NOT INLINE, inlining reply() in combination with compiler optimizations causes function breakup into
-// parts and the ICACHE_RAM_ATTR isn't propagated correctly to all parts, which of course causes crashes.
+// parts and the IRAM_ATTR isn't propagated correctly to all parts, which of course causes crashes.
 // TODO: test with gcc 9.x and if it still fails, disable optimization with -fdisable-ipa-fnsplit
-void ICACHE_RAM_ATTR Twi::reply(uint8_t ack)
+void IRAM_ATTR Twi::reply(uint8_t ack)
 {
     // transmit master read ready signal, with or without ack
     if (ack)
@@ -492,7 +492,7 @@ void ICACHE_RAM_ATTR Twi::reply(uint8_t ack)
 }
 
 
-void ICACHE_RAM_ATTR Twi::releaseBus(void)
+void IRAM_ATTR Twi::releaseBus(void)
 {
     // release bus
     //TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT);
@@ -505,7 +505,7 @@ void ICACHE_RAM_ATTR Twi::releaseBus(void)
 }
 
 
-void ICACHE_RAM_ATTR Twi::onTwipEvent(uint8_t status)
+void IRAM_ATTR Twi::onTwipEvent(uint8_t status)
 {
     twip_status = status;
     switch (status)
@@ -612,7 +612,7 @@ void ICACHE_RAM_ATTR Twi::onTwipEvent(uint8_t status)
     }
 }
 
-void ICACHE_RAM_ATTR Twi::onTimer(void *unused)
+void IRAM_ATTR Twi::onTimer(void *unused)
 {
     (void)unused;
     twi.releaseBus();
@@ -662,7 +662,7 @@ void Twi::eventTask(ETSEvent *e)
 // Shorthand for if the state is any of the or'd bitmask x
 #define IFSTATE(x) if (twip_state_mask & (x))
 
-void ICACHE_RAM_ATTR Twi::onSclChange(void)
+void IRAM_ATTR Twi::onSclChange(void)
 {
     unsigned int sda;
     unsigned int scl;
@@ -860,7 +860,7 @@ void ICACHE_RAM_ATTR Twi::onSclChange(void)
     }
 }
 
-void ICACHE_RAM_ATTR Twi::onSdaChange(void)
+void IRAM_ATTR Twi::onSdaChange(void)
 {
     unsigned int sda;
     unsigned int scl;

cores/esp8266/core_esp8266_timer.cpp

@@ -31,7 +31,7 @@ extern "C" {
 
 static volatile timercallback timer1_user_cb = NULL;
 
-void ICACHE_RAM_ATTR timer1_isr_handler(void *para, void *frame) {
+void IRAM_ATTR timer1_isr_handler(void *para, void *frame) {
     (void) para;
     (void) frame;
     if ((T1C & ((1 << TCAR) | (1 << TCIT))) == 0) TEIE &= ~TEIE1;//edge int disable
@@ -45,32 +45,32 @@ void ICACHE_RAM_ATTR timer1_isr_handler(void *para, void *frame) {
     }
 }
 
-void ICACHE_RAM_ATTR timer1_isr_init(){
+void IRAM_ATTR timer1_isr_init(){
     ETS_FRC_TIMER1_INTR_ATTACH(timer1_isr_handler, NULL);
 }
 
-void ICACHE_RAM_ATTR timer1_attachInterrupt(timercallback userFunc) {
+void IRAM_ATTR timer1_attachInterrupt(timercallback userFunc) {
     timer1_user_cb = userFunc;
     ETS_FRC1_INTR_ENABLE();
 }
 
-void ICACHE_RAM_ATTR timer1_detachInterrupt() {
+void IRAM_ATTR timer1_detachInterrupt() {
     timer1_user_cb = 0;
     TEIE &= ~TEIE1;//edge int disable
     ETS_FRC1_INTR_DISABLE();
 }
 
-void ICACHE_RAM_ATTR timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
+void IRAM_ATTR timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
     T1C = (1 << TCTE) | ((divider & 3) << TCPD) | ((int_type & 1) << TCIT) | ((reload & 1) << TCAR);
     T1I = 0;
 }
 
-void ICACHE_RAM_ATTR timer1_write(uint32_t ticks){
+void IRAM_ATTR timer1_write(uint32_t ticks){
     T1L = ((ticks)& 0x7FFFFF);
     if ((T1C & (1 << TCIT)) == 0) TEIE |= TEIE1;//edge int enable
 }
 
-void ICACHE_RAM_ATTR timer1_disable(){
+void IRAM_ATTR timer1_disable(){
     T1C = 0;
     T1I = 0;
 }
@@ -80,7 +80,7 @@ void ICACHE_RAM_ATTR timer1_disable(){
 
 static volatile timercallback timer0_user_cb = NULL;
 
-void ICACHE_RAM_ATTR timer0_isr_handler(void *para, void *frame) {
+void IRAM_ATTR timer0_isr_handler(void *para, void *frame) {
     (void) para;
     (void) frame;
     if (timer0_user_cb) {
@@ -92,16 +92,16 @@ void ICACHE_RAM_ATTR timer0_isr_handler(void *para, void *frame) {
     }
 }
 
-void ICACHE_RAM_ATTR timer0_isr_init(){
+void IRAM_ATTR timer0_isr_init(){
     ETS_CCOMPARE0_INTR_ATTACH(timer0_isr_handler, NULL);
 }
 
-void ICACHE_RAM_ATTR timer0_attachInterrupt(timercallback userFunc) {
+void IRAM_ATTR timer0_attachInterrupt(timercallback userFunc) {
     timer0_user_cb = userFunc;
     ETS_CCOMPARE0_ENABLE();
 }
 
-void ICACHE_RAM_ATTR timer0_detachInterrupt() {
+void IRAM_ATTR timer0_detachInterrupt() {
     timer0_user_cb = NULL;
     ETS_CCOMPARE0_DISABLE();
 }

cores/esp8266/core_esp8266_waveform.h

@@ -112,7 +112,7 @@ int stopWaveform(uint8_t pin);
 // to determine whether or not to perform an operation.
 // Pass in NULL to disable the callback and, if no other waveforms being
 // generated, stop the timer as well.
-// Make sure the CB function has the ICACHE_RAM_ATTR decorator.
+// Make sure the CB function has the IRAM_ATTR decorator.
 void setTimer1Callback(uint32_t (*fn)());
 
 

cores/esp8266/core_esp8266_waveform_phase.cpp

@@ -111,7 +111,7 @@ namespace {
 }
 
 // Interrupt on/off control
-static ICACHE_RAM_ATTR void timer1Interrupt();
+static IRAM_ATTR void timer1Interrupt();
 
 // Non-speed critical bits
 #pragma GCC optimize ("Os")
@@ -125,7 +125,7 @@ static void initTimer() {
   timer1_write(IRQLATENCYCCYS); // Cause an interrupt post-haste
 }
 
-static void ICACHE_RAM_ATTR deinitTimer() {
+static void IRAM_ATTR deinitTimer() {
   ETS_FRC_TIMER1_NMI_INTR_ATTACH(NULL);
   timer1_disable();
   timer1_isr_init();
@@ -218,7 +218,7 @@ int startWaveformClockCycles_weak(uint8_t pin, uint32_t highCcys, uint32_t lowCc
 }
 
 // Stops a waveform on a pin
-ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
+IRAM_ATTR int stopWaveform_weak(uint8_t pin) {
   // Can't possibly need to stop anything if there is no timer active
   if (!waveform.timer1Running) {
     return false;
@@ -252,7 +252,7 @@ ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
 
 // For dynamic CPU clock frequency switch in loop the scaling logic would have to be adapted.
 // Using constexpr makes sure that the CPU clock frequency is compile-time fixed.
-static inline ICACHE_RAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool isCPU2X) {
+static inline IRAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool isCPU2X) {
   if (ISCPUFREQ160MHZ) {
     return isCPU2X ? ccys : (ccys >> 1);
   }
@@ -261,7 +261,7 @@ static inline ICACHE_RAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool i
   }
 }
 
-static ICACHE_RAM_ATTR void timer1Interrupt() {
+static IRAM_ATTR void timer1Interrupt() {
   const uint32_t isrStartCcy = ESP.getCycleCount();
   int32_t clockDrift = isrStartCcy - waveform.nextEventCcy;
   const bool isCPU2X = CPU2X & 1;