diff --git a/esp32-hal/examples/rtc_watchdog.rs b/esp32-hal/examples/rtc_watchdog.rs
new file mode 100644
index 00000000000..45041da7568
--- /dev/null
+++ b/esp32-hal/examples/rtc_watchdog.rs
@@ -0,0 +1,66 @@
+//! This demos the RTC Watchdog Timer (RWDT).
+//! The RWDT is initially configured to trigger an interrupt after a given
+//! timeout. Then, upon expiration, the RWDT is restarted and then reconfigured
+//! to reset both the main system and the RTC.
+
+#![no_std]
+#![no_main]
+
+use core::cell::RefCell;
+
+use esp32_hal::{
+    clock::ClockControl,
+    interrupt,
+    pac::{self, Peripherals},
+    prelude::*,
+    Rtc,
+    Rwdt,
+};
+use panic_halt as _;
+use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
+use xtensa_lx_rt::entry;
+
+static mut RWDT: CriticalSectionMutex<RefCell<Option<Rwdt>>> =
+    CriticalSectionMutex::new(RefCell::new(None));
+
+#[entry]
+fn main() -> ! {
+    let peripherals = Peripherals::take().unwrap();
+    let system = peripherals.DPORT.split();
+    let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
+
+    let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+
+    // Disable watchdog timer
+    rtc.rwdt.disable();
+
+    rtc.rwdt.start(2000u64.millis());
+    rtc.rwdt.listen();
+
+    interrupt::enable(pac::Interrupt::RTC_CORE, interrupt::Priority::Priority1).unwrap();
+
+    unsafe {
+        (&RWDT).lock(|data| (*data).replace(Some(rtc.rwdt)));
+    }
+
+    loop {}
+}
+
+#[interrupt]
+fn RTC_CORE() {
+    unsafe {
+        (&RWDT).lock(|data| {
+            esp_println::println!("RWDT Interrupt");
+
+            let mut rwdt = data.borrow_mut();
+            let rwdt = rwdt.as_mut().unwrap();
+
+            rwdt.clear_interrupt();
+
+            esp_println::println!("Restarting in 5 seconds...");
+
+            rwdt.start(5000u64.millis());
+            rwdt.unlisten();
+        });
+    }
+}
diff --git a/esp32-hal/src/lib.rs b/esp32-hal/src/lib.rs
index 8d17d1ab642..0c308647539 100644
--- a/esp32-hal/src/lib.rs
+++ b/esp32-hal/src/lib.rs
@@ -22,6 +22,7 @@ pub use esp_hal_common::{
     PulseControl,
     Rng,
     Rtc,
+    Rwdt,
     Serial,
 };
 
diff --git a/esp32c3-hal/examples/rtc_watchdog.rs b/esp32c3-hal/examples/rtc_watchdog.rs
index 785708f48c6..a5781617e84 100644
--- a/esp32c3-hal/examples/rtc_watchdog.rs
+++ b/esp32c3-hal/examples/rtc_watchdog.rs
@@ -15,9 +15,8 @@ use esp32c3_hal::{
     interrupt,
     pac::{self, Peripherals},
     prelude::*,
-    Rtc,
+    Rtc, Rwdt,
 };
-use esp_hal_common::Rwdt;
 use panic_halt as _;
 use riscv_rt::entry;
 
diff --git a/esp32c3-hal/src/lib.rs b/esp32c3-hal/src/lib.rs
index 634199c7fe9..0f606c5363d 100644
--- a/esp32c3-hal/src/lib.rs
+++ b/esp32c3-hal/src/lib.rs
@@ -4,28 +4,8 @@ use core::arch::global_asm;
 
 pub use embedded_hal as ehal;
 pub use esp_hal_common::{
-    clock,
-    efuse,
-    gpio as gpio_types,
-    i2c,
-    interrupt,
-    ledc,
-    macros,
-    pac,
-    prelude,
-    pulse_control,
-    serial,
-    spi,
-    system,
-    systimer,
-    timer,
-    utils,
-    Cpu,
-    Delay,
-    PulseControl,
-    Rng,
-    Rtc,
-    Serial,
+    clock, efuse, gpio as gpio_types, i2c, interrupt, ledc, macros, pac, prelude, pulse_control,
+    serial, spi, system, systimer, timer, utils, Cpu, Delay, PulseControl, Rng, Rtc, Rwdt, Serial,
     UsbSerialJtag,
 };
 #[cfg(feature = "direct-boot")]
diff --git a/esp32s2-hal/examples/rtc_watchdog.rs b/esp32s2-hal/examples/rtc_watchdog.rs
new file mode 100644
index 00000000000..aa3b80d28a5
--- /dev/null
+++ b/esp32s2-hal/examples/rtc_watchdog.rs
@@ -0,0 +1,66 @@
+//! This demos the RTC Watchdog Timer (RWDT).
+//! The RWDT is initially configured to trigger an interrupt after a given
+//! timeout. Then, upon expiration, the RWDT is restarted and then reconfigured
+//! to reset both the main system and the RTC.
+
+#![no_std]
+#![no_main]
+
+use core::cell::RefCell;
+
+use esp32s2_hal::{
+    clock::ClockControl,
+    interrupt,
+    pac::{self, Peripherals},
+    prelude::*,
+    Rtc,
+    Rwdt,
+};
+use panic_halt as _;
+use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
+use xtensa_lx_rt::entry;
+
+static mut RWDT: CriticalSectionMutex<RefCell<Option<Rwdt>>> =
+    CriticalSectionMutex::new(RefCell::new(None));
+
+#[entry]
+fn main() -> ! {
+    let peripherals = Peripherals::take().unwrap();
+    let system = peripherals.SYSTEM.split();
+    let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
+
+    let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+
+    // Disable watchdog timer
+    rtc.rwdt.disable();
+
+    rtc.rwdt.start(2000u64.millis());
+    rtc.rwdt.listen();
+
+    interrupt::enable(pac::Interrupt::RTC_CORE, interrupt::Priority::Priority1).unwrap();
+
+    unsafe {
+        (&RWDT).lock(|data| (*data).replace(Some(rtc.rwdt)));
+    }
+
+    loop {}
+}
+
+#[interrupt]
+fn RTC_CORE() {
+    unsafe {
+        (&RWDT).lock(|data| {
+            esp_println::println!("RWDT Interrupt");
+
+            let mut rwdt = data.borrow_mut();
+            let rwdt = rwdt.as_mut().unwrap();
+
+            rwdt.clear_interrupt();
+
+            esp_println::println!("Restarting in 5 seconds...");
+
+            rwdt.start(5000u64.millis());
+            rwdt.unlisten();
+        });
+    }
+}
diff --git a/esp32s2-hal/src/lib.rs b/esp32s2-hal/src/lib.rs
index ee9802d72d0..2f5e4a41bf0 100644
--- a/esp32s2-hal/src/lib.rs
+++ b/esp32s2-hal/src/lib.rs
@@ -22,6 +22,7 @@ pub use esp_hal_common::{
     PulseControl,
     Rng,
     Rtc,
+    Rwdt,
     Serial,
 };
 
diff --git a/esp32s3-hal/examples/rtc_watchdog.rs b/esp32s3-hal/examples/rtc_watchdog.rs
new file mode 100644
index 00000000000..a4407837712
--- /dev/null
+++ b/esp32s3-hal/examples/rtc_watchdog.rs
@@ -0,0 +1,67 @@
+//! This demos the RTC Watchdog Timer (RWDT).
+//! The RWDT is initially configured to trigger an interrupt after a given
+//! timeout. Then, upon expiration, the RWDT is restarted and then reconfigured
+//! to reset both the main system and the RTC.
+
+#![no_std]
+#![no_main]
+
+use core::cell::RefCell;
+
+use esp32s3_hal::{
+    clock::ClockControl,
+    interrupt,
+    pac::{self, Peripherals},
+    prelude::*,
+    Rtc,
+    Rwdt,
+};
+use panic_halt as _;
+use xtensa_lx::mutex::{CriticalSectionMutex, Mutex};
+use xtensa_lx_rt::entry;
+
+static mut RWDT: CriticalSectionMutex<RefCell<Option<Rwdt>>> =
+    CriticalSectionMutex::new(RefCell::new(None));
+
+#[entry]
+fn main() -> ! {
+    let peripherals = Peripherals::take().unwrap();
+    let system = peripherals.SYSTEM.split();
+    let _clocks = ClockControl::boot_defaults(system.clock_control).freeze();
+
+    let mut rtc = Rtc::new(peripherals.RTC_CNTL);
+
+    // Disable watchdog timers
+    rtc.swd.disable();
+    rtc.rwdt.disable();
+
+    rtc.rwdt.start(2000u64.millis());
+    rtc.rwdt.listen();
+
+    interrupt::enable(pac::Interrupt::RTC_CORE, interrupt::Priority::Priority1).unwrap();
+
+    unsafe {
+        (&RWDT).lock(|data| (*data).replace(Some(rtc.rwdt)));
+    }
+
+    loop {}
+}
+
+#[interrupt]
+fn RTC_CORE() {
+    unsafe {
+        (&RWDT).lock(|data| {
+            esp_println::println!("RWDT Interrupt");
+
+            let mut rwdt = data.borrow_mut();
+            let rwdt = rwdt.as_mut().unwrap();
+
+            rwdt.clear_interrupt();
+
+            esp_println::println!("Restarting in 5 seconds...");
+
+            rwdt.start(5000u64.millis());
+            rwdt.unlisten();
+        });
+    }
+}
diff --git a/esp32s3-hal/src/lib.rs b/esp32s3-hal/src/lib.rs
index 6440fc0216b..9b3b2b2ce81 100644
--- a/esp32s3-hal/src/lib.rs
+++ b/esp32s3-hal/src/lib.rs
@@ -26,6 +26,7 @@ pub use esp_hal_common::{
     PulseControl,
     Rng,
     Rtc,
+    Rwdt,
     Serial,
     UsbSerialJtag,
 };