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Verilog .init files currently have to be copied to the build/gateware directory which require workaround for external cores coming with their .init files.
The text was updated successfully, but these errors were encountered:
Verilog .init files currently have to be copied to the
build/gateware
directory which require workaround for external cores coming with their .init files.The text was updated successfully, but these errors were encountered: