From 2ff6583f136d9b8a08453cfb87bef6598690c5d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 30 Sep 2024 12:49:04 +0200 Subject: [PATCH] build: efinix: common: allow different in clk on reg Tristates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit allow a different clk for input on registered Tristates. Signed-off-by: Fin Maaß --- litex/build/efinix/common.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py index 34e7ef7982..0e1b23d6f4 100644 --- a/litex/build/efinix/common.py +++ b/litex/build/efinix/common.py @@ -275,7 +275,7 @@ def lower(dr): # Efinix DDRTristate ------------------------------------------------------------------------------- class EfinixDDRTristateImpl(LiteXModule): - def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, out_clk_inv=False, in_clk_inv=False): + def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, out_clk_inv=False, in_clk_inv=False, in_clk=None): assert oe1 == oe2 assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform @@ -301,7 +301,7 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, out_clk_inv=False, in_clk_ "properties" : io_prop, "size" : 1, "in_reg" : "DDIO_RESYNC", - "in_clk_pin" : clk, + "in_clk_pin" : clk if in_clk is None else in_clk, "out_reg" : "DDIO_RESYNC", "out_clk_pin" : clk, "oe_reg" : "REG", @@ -320,7 +320,7 @@ def lower(dr): # Efinix SDRTristate ------------------------------------------------------------------------------- class EfinixSDRTristateImpl(LiteXModule): - def __init__(self, io, o, oe, i, clk, out_clk_inv=False, in_clk_inv=False): + def __init__(self, io, o, oe, i, clk, out_clk_inv=False, in_clk_inv=False, in_clk=None): assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform io_name = platform.get_pin_name(io) @@ -341,7 +341,7 @@ def __init__(self, io, o, oe, i, clk, out_clk_inv=False, in_clk_inv=False): "properties" : io_prop, "size" : 1, "in_reg" : "REG", - "in_clk_pin" : clk, + "in_clk_pin" : clk if in_clk is None else in_clk, "out_reg" : "REG", "out_clk_pin" : clk, "oe_reg" : "REG",