From 0bd77b92ab49e4c4ca6a3d8e3b106be1d8b54452 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fin=20Maa=C3=9F?= Date: Mon, 30 Sep 2024 12:45:13 +0200 Subject: [PATCH] build efinix: common: allow clk inverting on registered gpio MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit allow clk inverting on registered gpio. Signed-off-by: Fin Maaß --- litex/build/efinix/common.py | 40 ++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/litex/build/efinix/common.py b/litex/build/efinix/common.py index c2f05401f7..34e7ef7982 100644 --- a/litex/build/efinix/common.py +++ b/litex/build/efinix/common.py @@ -275,7 +275,7 @@ def lower(dr): # Efinix DDRTristate ------------------------------------------------------------------------------- class EfinixDDRTristateImpl(LiteXModule): - def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): + def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk, out_clk_inv=False, in_clk_inv=False): assert oe1 == oe2 assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform @@ -305,8 +305,8 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): "out_reg" : "DDIO_RESYNC", "out_clk_pin" : clk, "oe_reg" : "REG", - "in_clk_inv" : 0, - "out_clk_inv" : 0, + "in_clk_inv" : 1 if in_clk_inv else 0, + "out_clk_inv" : 1 if out_clk_inv else 0, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } platform.toolchain.ifacewriter.blocks.append(block) @@ -315,12 +315,12 @@ def __init__(self, io, o1, o2, oe1, oe2, i1, i2, clk): class EfinixDDRTristate: @staticmethod def lower(dr): - return EfinixDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk) + return EfinixDDRTristateImpl(dr.io, dr.o1, dr.o2, dr.oe1, dr.oe2, dr.i1, dr.i2, dr.clk, **dr.kwargs) # Efinix SDRTristate ------------------------------------------------------------------------------- class EfinixSDRTristateImpl(LiteXModule): - def __init__(self, io, o, oe, i, clk): + def __init__(self, io, o, oe, i, clk, out_clk_inv=False, in_clk_inv=False): assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform io_name = platform.get_pin_name(io) @@ -345,8 +345,8 @@ def __init__(self, io, o, oe, i, clk): "out_reg" : "REG", "out_clk_pin" : clk, "oe_reg" : "REG", - "in_clk_inv" : 0, - "out_clk_inv" : 0, + "in_clk_inv" : 1 if in_clk_inv else 0, + "out_clk_inv" : 1 if out_clk_inv else 0, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } platform.toolchain.ifacewriter.blocks.append(block) @@ -356,12 +356,12 @@ def __init__(self, io, o, oe, i, clk): class EfinixSDRTristate(LiteXModule): @staticmethod def lower(dr): - return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk) + return EfinixSDRTristateImpl(dr.io, dr.o, dr.oe, dr.i, dr.clk, **dr.kwargs) # Efinix SDROutput --------------------------------------------------------------------------------- class EfinixSDROutputImpl(LiteXModule): - def __init__(self, i, o, clk): + def __init__(self, i, o, clk, out_clk_inv=False): assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform io_name = platform.get_pin_name(o) @@ -379,7 +379,7 @@ def __init__(self, i, o, clk): "size" : 1, "out_reg" : "REG", "out_clk_pin" : clk, - "out_clk_inv" : 0, + "out_clk_inv" : 1 if out_clk_inv else 0, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } platform.toolchain.ifacewriter.blocks.append(block) @@ -389,12 +389,12 @@ def __init__(self, i, o, clk): class EfinixSDROutput(LiteXModule): @staticmethod def lower(dr): - return EfinixSDROutputImpl(dr.i, dr.o, dr.clk) + return EfinixSDROutputImpl(dr.i, dr.o, dr.clk, **dr.kwargs) # Efinix DDROutput --------------------------------------------------------------------------------- class EfinixDDROutputImpl(LiteXModule): - def __init__(self, i1, i2, o, clk): + def __init__(self, i1, i2, o, clk, out_clk_inv=False): assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform io_name = platform.get_pin_name(o) @@ -414,7 +414,7 @@ def __init__(self, i1, i2, o, clk): "size" : 1, "out_reg" : "DDIO_RESYNC", "out_clk_pin" : clk, - "out_clk_inv" : 0, + "out_clk_inv" : 1 if out_clk_inv else 0, "drive_strength" : io_prop_dict.get("DRIVE_STRENGTH", "4") } platform.toolchain.ifacewriter.blocks.append(block) @@ -423,12 +423,12 @@ def __init__(self, i1, i2, o, clk): class EfinixDDROutput: @staticmethod def lower(dr): - return EfinixDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) + return EfinixDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk, **dr.kwargs) # Efinix SDRInput ---------------------------------------------------------------------------------- class EfinixSDRInputImpl(LiteXModule): - def __init__(self, i, o, clk): + def __init__(self, i, o, clk, in_clk_inv=False): assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform io_name = platform.get_pin_name(i) @@ -445,7 +445,7 @@ def __init__(self, i, o, clk): "size" : 1, "in_reg" : "REG", "in_clk_pin" : clk, - "in_clk_inv" : 0 + "in_clk_inv" : 1 if in_clk_inv else 0, } platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.excluded_ios.append(platform.get_pin(i)) @@ -453,12 +453,12 @@ def __init__(self, i, o, clk): class EfinixSDRInput: @staticmethod def lower(dr): - return EfinixSDRInputImpl(dr.i, dr.o, dr.clk) + return EfinixSDRInputImpl(dr.i, dr.o, dr.clk, **dr.kwargs) # Efinix DDRInput ---------------------------------------------------------------------------------- class EfinixDDRInputImpl(LiteXModule): - def __init__(self, i, o1, o2, clk): + def __init__(self, i, o1, o2, clk, in_clk_inv=False): assert_is_signal_or_clocksignal(clk) platform = LiteXContext.platform io_name = platform.get_pin_name(i) @@ -477,7 +477,7 @@ def __init__(self, i, o1, o2, clk): "size" : 1, "in_reg" : "DDIO_RESYNC", "in_clk_pin" : clk, - "in_clk_inv" : 0 + "in_clk_inv" : 1 if in_clk_inv else 0, } platform.toolchain.ifacewriter.blocks.append(block) platform.toolchain.excluded_ios.append(platform.get_pin(i)) @@ -485,7 +485,7 @@ def __init__(self, i, o1, o2, clk): class EfinixDDRInput: @staticmethod def lower(dr): - return EfinixDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk) + return EfinixDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk, **dr.kwargs) # Efinix Special Overrides -------------------------------------------------------------------------