diff --git a/CHANGES.md b/CHANGES.md
index e15f1288d6..e59eaf166b 100644
--- a/CHANGES.md
+++ b/CHANGES.md
@@ -11,6 +11,7 @@
 	- soc/cores/clock/colognechip   : Fixed and reworked locked signal handling.
 	- litesdcard                    : Fixed data_i sampling (https://github.com/enjoy-digital/litesdcard/pull/34).
 	- litespi/mmap                  : Fixed dummy bits (https://github.com/litex-hub/litespi/pull/71).
+	- sim/verilator                 : Fixed .fst empty dump with short simulation.
 
 	[> Added
 	--------
diff --git a/litex/build/sim/core/veril.cpp b/litex/build/sim/core/veril.cpp
index 2ea9a34823..5fc0b1f655 100644
--- a/litex/build/sim/core/veril.cpp
+++ b/litex/build/sim/core/veril.cpp
@@ -78,6 +78,8 @@ extern "C" void litex_sim_tracer_dump()
 
 extern "C" int litex_sim_got_finish()
 {
+  tfp->flush();
+  tfp->close();
   return Verilated::gotFinish();
 }