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Merge pull request #2082 from enjoy-digital/efinix_iface_signal_names ci #3298: Commit b11cc8c pushed by enjoy-digital
September 26, 2024 09:42 26m 6s master
master
September 26, 2024 09:42 26m 6s
Efinix iface signal names. ci #3297: Pull request #2082 synchronize by enjoy-digital
September 26, 2024 08:38 25m 15s efinix_iface_signal_names
efinix_iface_signal_names
September 26, 2024 08:38 25m 15s
build/efinix/common: Deprecate passing clk as str to avoid previous a… ci #3296: Commit 39d292a pushed by enjoy-digital
September 26, 2024 08:38 25m 13s efinix_iface_signal_names
efinix_iface_signal_names
September 26, 2024 08:38 25m 13s
Efinix iface signal names. ci #3295: Pull request #2082 opened by enjoy-digital
September 26, 2024 08:15 25m 50s efinix_iface_signal_names
efinix_iface_signal_names
September 26, 2024 08:15 25m 50s
build/efinix/common: Directly pass ClockSignal/Signal to blocks and l… ci #3294: Commit a3a55fc pushed by enjoy-digital
September 26, 2024 08:15 24m 43s efinix_iface_signal_names
efinix_iface_signal_names
September 26, 2024 08:15 24m 43s
build: efinix: common.py; add SDRInput ci #3293: Pull request #2081 opened by maass-hamburg
September 25, 2024 15:20 25m 36s VOGL-electronic:build_efinix_add_sdr_input
VOGL-electronic:build_efinix_add_sdr_input
September 25, 2024 15:20 25m 36s
build: efinix: ifacewriter: some fixes ci #3292: Pull request #2079 opened by maass-hamburg
September 25, 2024 09:13 24m 58s VOGL-electronic:efinix_iface_fixups
VOGL-electronic:efinix_iface_fixups
September 25, 2024 09:13 24m 58s
soc/cores/vexriscv_smp: Add the generation of the default sim config … ci #3291: Commit c3e8736 pushed by Dolu1990
September 25, 2024 08:38 24m 50s master
master
September 25, 2024 08:38 24m 50s
build/sim/core/veril.cpp: Flush trace file on finish, fix issue with … ci #3290: Commit b86d76b pushed by enjoy-digital
September 25, 2024 06:57 24m 31s master
master
September 25, 2024 06:57 24m 31s
build/sim/core/veril.cpp: Flush and close trace file on finish, fix i… ci #3289: Commit 00f72e1 pushed by enjoy-digital
September 25, 2024 06:54 25m 45s master
master
September 25, 2024 06:54 25m 45s
build: efinix: add function to add ip ci #3288: Pull request #2078 opened by maass-hamburg
September 24, 2024 10:01 25m 6s VOGL-electronic:efinix_add_ipm
VOGL-electronic:efinix_add_ipm
September 24, 2024 10:01 25m 6s
soc/interconnect/stream: Add Delay module. ci #3287: Commit c95a6e0 pushed by enjoy-digital
September 23, 2024 10:23 24m 53s master
master
September 23, 2024 10:23 24m 53s
CHANGES.md: Update. ci #3286: Commit b2f63b3 pushed by enjoy-digital
September 20, 2024 11:00 24m 31s master
master
September 20, 2024 11:00 24m 31s
build: io.py: add QDR input, output and tristate ci #3285: Pull request #2077 synchronize by maass-hamburg
September 19, 2024 13:13 25m 18s VOGL-electronic:add_qdr_gpios
VOGL-electronic:add_qdr_gpios
September 19, 2024 13:13 25m 18s
Merge pull request #2075 from trabucayre/efinix_clkinput_signal ci #3284: Commit baff4c6 pushed by enjoy-digital
September 19, 2024 09:59 24m 48s master
master
September 19, 2024 09:59 24m 48s
Merge pull request #2076 from trabucayre/xc7s_jtag ci #3283: Commit 033ec13 pushed by enjoy-digital
September 19, 2024 09:53 24m 45s master
master
September 19, 2024 09:53 24m 45s
build: io.py: add QDR input, output and tristate ci #3282: Pull request #2077 opened by maass-hamburg
September 19, 2024 09:14 25m 10s VOGL-electronic:add_qdr_gpios
VOGL-electronic:add_qdr_gpios
September 19, 2024 09:14 25m 10s
soc/core/hyperbus: Avoid combinatorial loop on write bursts (Reported… ci #3281: Commit 6e9dffd pushed by enjoy-digital
September 19, 2024 09:11 25m 29s master
master
September 19, 2024 09:11 25m 29s
soc/cores/cpu/vexiirscv: Add standard variant to allow compilation wi… ci #3280: Commit ad2c3fc pushed by enjoy-digital
September 19, 2024 07:21 27m 40s master
master
September 19, 2024 07:21 27m 40s
build/efinix/common.py: ClkInput: added ClockSignal support ci #3279: Pull request #2075 synchronize by trabucayre
September 19, 2024 07:14 27m 24s trabucayre:efinix_clkinput_signal
trabucayre:efinix_clkinput_signal
September 19, 2024 07:14 27m 24s
Spartan7 jtag support ci #3278: Pull request #2076 opened by trabucayre
September 19, 2024 04:50 26m 53s trabucayre:xc7s_jtag
trabucayre:xc7s_jtag
September 19, 2024 04:50 26m 53s
build/efinix/common.py: ClkInput: added ClockSignal support ci #3277: Pull request #2075 opened by trabucayre
September 18, 2024 13:27 27m 1s trabucayre:efinix_clkinput_signal
trabucayre:efinix_clkinput_signal
September 18, 2024 13:27 27m 1s
build: io.py: DDRTristate: check oe2 ci #3276: Pull request #2074 opened by maass-hamburg
September 18, 2024 13:08 25m 47s VOGL-electronic:ddrtristate_oe2_ckeck
VOGL-electronic:ddrtristate_oe2_ckeck
September 18, 2024 13:08 25m 47s
build: io: make oe2 of DDRTristate optional ci #3275: Pull request #2068 synchronize by maass-hamburg
September 18, 2024 13:06 24m 54s VOGL-electronic:ddrtristate_oe2_optional
VOGL-electronic:ddrtristate_oe2_optional
September 18, 2024 13:06 24m 54s
Merge pull request #1974 from motec-research/dts_zephyr_updates ci #3274: Commit 9bacbe1 pushed by enjoy-digital
September 17, 2024 12:58 26m 11s master
master
September 17, 2024 12:58 26m 11s