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1 parent e018257 commit 9460834Copy full SHA for 9460834
litesdcard/core.py
@@ -24,6 +24,7 @@ class SDCore(LiteXModule):
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def __init__(self, phy):
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self.sink = stream.Endpoint([("data", 8)])
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self.source = stream.Endpoint([("data", 8)])
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+ self.irq = Signal()
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# Cmd Registers.
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self.cmd_argument = CSRStorage(32, description="SDCard Cmd Argument.")
@@ -115,6 +116,11 @@ def __init__(self, phy):
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crc7_inserter.enable.eq(1),
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]
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+ # IRQ / Generate IRQ on CMD done rising edge
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+ done_d = Signal()
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+ self.sync += done_d.eq(cmd_done)
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+ self.sync += self.irq.eq(cmd_done & ~done_d)
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+
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# Main FSM ---------------------------------------------------------------------------------
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self.fsm = fsm = FSM()
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fsm.act("IDLE",
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