@@ -18,8 +18,8 @@ class TestPHY(unittest.TestCase):
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def test_clocker_div2 (self ):
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def gen (dut ):
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yield dut .divider .storage .eq (2 )
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- clk = "__ -_-_-_-_-_-_-_"
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- ce = "_ -_-_-_-_-_-_-_-"
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+ clk = "____ -_-_-_-_-_-_-_"
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+ ce = "___ -_-_-_-_-_-_-_-"
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for i in range (len (clk )):
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self .assertEqual (c2bool (clk [i ]), (yield dut .clk ))
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self .assertEqual (c2bool (ce [i ]), (yield dut .ce ))
@@ -30,8 +30,8 @@ def gen(dut):
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def test_clocker_div4 (self ):
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def gen (dut ):
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yield dut .divider .storage .eq (4 )
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- clk = "____ --__--__--__-"
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- ce = "__ -___-___-___-__"
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+ clk = "______ --__--__--__-"
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+ ce = "____ -___-___-___-__"
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for i in range (len (clk )):
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self .assertEqual (c2bool (clk [i ]), (yield dut .clk ))
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self .assertEqual (c2bool (ce [i ]), (yield dut .ce ))
@@ -42,8 +42,8 @@ def gen(dut):
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def test_clocker_div8 (self ):
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def gen (dut ):
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yield dut .divider .storage .eq (8 )
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- clk = "________ ----____----"
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- ce = "____ -_______-_______"
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+ clk = "__________ ----____----"
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+ ce = "______ -_______-_______"
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for i in range (len (clk )):
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self .assertEqual (c2bool (clk [i ]), (yield dut .clk ))
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self .assertEqual (c2bool (ce [i ]), (yield dut .ce ))
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