From 3c9b2410dee3f114dad7450d6e0ec733369b4a98 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 7 Nov 2023 15:25:24 +0100 Subject: [PATCH] phy: Use BUFG on Xilinx devices to route clocker.ce to improve timings. --- litesdcard/phy.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/litesdcard/phy.py b/litesdcard/phy.py index e8283f6..2040f93 100644 --- a/litesdcard/phy.py +++ b/litesdcard/phy.py @@ -61,7 +61,14 @@ def __init__(self): for i in range(2, 9): cases[2**i] = clk.eq(clks[i-1]) self.comb += Case(self.divider.storage, cases) - self.comb += self.ce.eq(clk & ~clk_d) + + # FIXME: Use BUFG to improve timings on large Xilinx desings, try to improve and make it more generic. + from litex.gen import LiteXContext + from litex.build.xilinx import XilinxPlatform + if isinstance(LiteXContext.platform, XilinxPlatform): + self.specials += Instance("BUFG", i_I=clk & ~clk_d, o_O=self.ce) + else: + self.comb += self.ce.eq(clk & ~clk_d) # Ensure we don't get short pulses on the SDCard Clk. ce_delayed = Signal()