--- pu32-orangecrab0225/litedram/litedram_native.v	2023-05-07 21:42:15.056725924 -0500
+++ pu32-orangecrab0225/litedram/litedram.v	2023-05-07 21:42:09.541969887 -0500
@@ -9,7 +9,7 @@
 // Filename   : litedram_core.v
 // Device     : LFE5U-25F-8MG285C
 // LiteX sha1 : a4cc859d
-// Date       : 2023-05-07 21:36:35
+// Date       : 2023-04-24 22:46:16
 //------------------------------------------------------------------------------
 /* Generated using:
    git revert 6755c84 bd80053
@@ -47,8 +47,8 @@
 
     # User Ports ---------------------------------------------------------------
     "user_ports": {
-        "native_0" : {
-            "type": "native",
+        "wishbone_0" : {
+            "type": "wishbone",
         },
     },
 }*/
@@ -90,17 +90,15 @@
 	output wire wb_ctrl_err,
 	output wire user_clk,
 	output wire user_rst,
-	input  wire user_port_native_0_cmd_valid,
-	output wire user_port_native_0_cmd_ready,
-	input  wire user_port_native_0_cmd_we,
-	input  wire [22:0] user_port_native_0_cmd_addr,
-	input  wire user_port_native_0_wdata_valid,
-	output wire user_port_native_0_wdata_ready,
-	input  wire [15:0] user_port_native_0_wdata_we,
-	input  wire [127:0] user_port_native_0_wdata_data,
-	output wire user_port_native_0_rdata_valid,
-	input  wire user_port_native_0_rdata_ready,
-	output wire [127:0] user_port_native_0_rdata_data
+	input  wire [22:0] user_port_wishbone_0_adr,
+	input  wire [127:0] user_port_wishbone_0_dat_w,
+	output wire [127:0] user_port_wishbone_0_dat_r,
+	input  wire [15:0] user_port_wishbone_0_sel,
+	input  wire user_port_wishbone_0_cyc,
+	input  wire user_port_wishbone_0_stb,
+	output wire user_port_wishbone_0_ack,
+	input  wire user_port_wishbone_0_we,
+	output wire user_port_wishbone_0_err
 );
 
 
@@ -1545,8 +1543,10 @@
 wire [1:0] wb_bus_bte;
 wire wb_bus_err;
 reg  user_enable = 1'd0;
+wire user_port_flush;
 wire user_port_cmd_valid;
 wire user_port_cmd_ready;
+wire user_port_cmd_last;
 wire user_port_cmd_payload_we;
 wire [22:0] user_port_cmd_payload_addr;
 wire user_port_wdata_valid;
@@ -1556,6 +1556,20 @@
 wire user_port_rdata_valid;
 wire user_port_rdata_ready;
 wire [127:0] user_port_rdata_payload_data;
+wire [22:0] wb_port_adr;
+wire [127:0] wb_port_dat_w;
+wire [127:0] wb_port_dat_r;
+wire [15:0] wb_port_sel;
+wire wb_port_cyc;
+wire wb_port_stb;
+wire wb_port_ack;
+wire wb_port_we;
+reg  wb_port_err = 1'd0;
+reg  cmd_consumed = 1'd0;
+reg  wdata_consumed = 1'd0;
+wire ack_cmd;
+wire ack_wdata;
+wire ack_rdata;
 wire litedramecp5ddrphycrg_ecp5pll;
 wire litedramecp5ddrphycrg_locked;
 reg  [1:0] litedramcore_refresher_state = 2'd0;
@@ -1831,17 +1845,15 @@
 assign wb_ctrl_err = wb_bus_err;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign user_port_cmd_valid = (user_port_native_0_cmd_valid & user_enable);
-assign user_port_native_0_cmd_ready = (user_port_cmd_ready & user_enable);
-assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
-assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign user_port_wdata_valid = (user_port_native_0_wdata_valid & user_enable);
-assign user_port_native_0_wdata_ready = (user_port_wdata_ready & user_enable);
-assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
-assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = (user_port_rdata_valid & user_enable);
-assign user_port_rdata_ready = (user_port_native_0_rdata_ready & user_enable);
-assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign wb_port_adr = user_port_wishbone_0_adr;
+assign wb_port_dat_w = user_port_wishbone_0_dat_w;
+assign user_port_wishbone_0_dat_r = wb_port_dat_r;
+assign wb_port_sel = user_port_wishbone_0_sel;
+assign wb_port_cyc = (user_port_wishbone_0_cyc & user_enable);
+assign wb_port_stb = (user_port_wishbone_0_stb & user_enable);
+assign user_port_wishbone_0_ack = (wb_port_ack & user_enable);
+assign wb_port_we = user_port_wishbone_0_we;
+assign user_port_wishbone_0_err = wb_port_err;
 assign por_clk = clk;
 assign crg_por_done = (crg_por_count == 1'd0);
 assign crg_reset1 = (((~crg_por_done) | rst) | crg_rst);
@@ -4624,7 +4636,7 @@
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
@@ -4646,7 +4658,7 @@
 						if (litedramcore_bankmachine2_row_hit) begin
 							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
 							end else begin
-								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
 							end
 						end else begin
 						end
@@ -4658,7 +4670,7 @@
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
@@ -4679,8 +4691,8 @@
 					if (litedramcore_bankmachine2_row_opened) begin
 						if (litedramcore_bankmachine2_row_hit) begin
 							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
+								litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -4692,7 +4704,7 @@
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
@@ -4713,7 +4725,7 @@
 					if (litedramcore_bankmachine2_row_opened) begin
 						if (litedramcore_bankmachine2_row_hit) begin
 							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+								litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -4726,7 +4738,7 @@
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (litedramcore_bankmachine2_state)
 		1'd1: begin
 		end
@@ -4747,8 +4759,8 @@
 					if (litedramcore_bankmachine2_row_opened) begin
 						if (litedramcore_bankmachine2_row_hit) begin
 							if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
 							end else begin
-								litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
 							end
 						end else begin
 						end
@@ -4962,6 +4974,40 @@
 	endcase
 end
 always @(*) begin
+	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (litedramcore_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		default: begin
+			if (litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (litedramcore_bankmachine3_row_opened) begin
+						if (litedramcore_bankmachine3_row_hit) begin
+							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+end
+always @(*) begin
 	litedramcore_bankmachine3_row_close <= 1'd0;
 	case (litedramcore_bankmachine3_state)
 		1'd1: begin
@@ -5159,40 +5205,6 @@
 	endcase
 end
 always @(*) begin
-	litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
-	case (litedramcore_bankmachine3_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		default: begin
-			if (litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (litedramcore_bankmachine3_row_opened) begin
-						if (litedramcore_bankmachine3_row_hit) begin
-							if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-end
-always @(*) begin
 	litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (litedramcore_bankmachine3_state)
 		1'd1: begin
@@ -8017,6 +8029,20 @@
 assign litedramcore_roundrobin5_grant = 1'd0;
 assign litedramcore_roundrobin6_grant = 1'd0;
 assign litedramcore_roundrobin7_grant = 1'd0;
+assign user_port_cmd_payload_addr = (wb_port_adr - 1'd0);
+assign user_port_cmd_payload_we = wb_port_we;
+assign user_port_wdata_payload_data = wb_port_dat_w;
+assign user_port_wdata_payload_we = wb_port_sel;
+assign wb_port_dat_r = user_port_rdata_payload_data;
+assign user_port_flush = (~wb_port_cyc);
+assign user_port_cmd_last = (~wb_port_we);
+assign user_port_cmd_valid = ((wb_port_cyc & wb_port_stb) & (~cmd_consumed));
+assign user_port_wdata_valid = (((user_port_cmd_valid | cmd_consumed) & user_port_cmd_payload_we) & (~wdata_consumed));
+assign user_port_rdata_ready = ((user_port_cmd_valid | cmd_consumed) & (~user_port_cmd_payload_we));
+assign wb_port_ack = (ack_cmd & ((wb_port_we & ack_wdata) | ((~wb_port_we) & ack_rdata)));
+assign ack_cmd = ((user_port_cmd_valid & user_port_cmd_ready) | cmd_consumed);
+assign ack_wdata = ((user_port_wdata_valid & user_port_wdata_ready) | wdata_consumed);
+assign ack_rdata = (user_port_rdata_valid & user_port_rdata_ready);
 always @(*) begin
 	next_state <= 2'd0;
 	next_state <= state;
@@ -8035,110 +8061,110 @@
 	endcase
 end
 always @(*) begin
-	litedramcore_dat_w_next_value0 <= 32'd0;
+	litedramcore_adr_next_value_ce1 <= 1'd0;
 	case (state)
 		1'd1: begin
+			litedramcore_adr_next_value_ce1 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	litedramcore_we_next_value2 <= 1'd0;
 	case (state)
 		1'd1: begin
+			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
 		end
 		default: begin
-			litedramcore_dat_w_next_value_ce0 <= 1'd1;
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value1 <= 14'd0;
+	litedramcore_wishbone_dat_r <= 32'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
-			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_adr_next_value_ce1 <= 1'd0;
+	litedramcore_we_next_value_ce2 <= 1'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_adr_next_value_ce1 <= 1'd1;
+			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
 			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value_ce1 <= 1'd1;
+				litedramcore_we_next_value_ce2 <= 1'd1;
 			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value2 <= 1'd0;
+	litedramcore_wishbone_ack <= 1'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_we_next_value2 <= 1'd0;
 		end
 		2'd2: begin
+			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
-			end
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_dat_r <= 32'd0;
+	litedramcore_dat_w_next_value0 <= 32'd0;
 	case (state)
 		1'd1: begin
 		end
 		2'd2: begin
-			litedramcore_wishbone_dat_r <= litedramcore_dat_r;
 		end
 		default: begin
+			litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_we_next_value_ce2 <= 1'd0;
+	litedramcore_dat_w_next_value_ce0 <= 1'd0;
 	case (state)
 		1'd1: begin
-			litedramcore_we_next_value_ce2 <= 1'd1;
 		end
 		2'd2: begin
 		end
 		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_we_next_value_ce2 <= 1'd1;
-			end
+			litedramcore_dat_w_next_value_ce0 <= 1'd1;
 		end
 	endcase
 end
 always @(*) begin
-	litedramcore_wishbone_ack <= 1'd0;
+	litedramcore_adr_next_value1 <= 14'd0;
 	case (state)
 		1'd1: begin
+			litedramcore_adr_next_value1 <= 1'd0;
 		end
 		2'd2: begin
-			litedramcore_wishbone_ack <= 1'd1;
 		end
 		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+			end
 		end
 	endcase
 end
@@ -8169,15 +8195,15 @@
 end
 assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
-	csrbank0_init_error0_re <= 1'd0;
+	csrbank0_init_error0_we <= 1'd0;
 	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank0_init_error0_re <= interface0_bank_bus_we;
+		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank0_init_error0_we <= 1'd0;
+	csrbank0_init_error0_re <= 1'd0;
 	if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+		csrbank0_init_error0_re <= interface0_bank_bus_we;
 	end
 end
 assign csrbank0_init_done0_w = init_done_storage;
@@ -8185,15 +8211,15 @@
 assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
 assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
 always @(*) begin
-	csrbank1_dly_sel0_re <= 1'd0;
+	csrbank1_dly_sel0_we <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dly_sel0_we <= 1'd0;
+	csrbank1_dly_sel0_re <= 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+		csrbank1_dly_sel0_re <= interface1_bank_bus_we;
 	end
 end
 assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
@@ -8293,15 +8319,15 @@
 end
 assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank2_dfii_pi0_command0_re <= 1'd0;
+	csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_command0_we <= 1'd0;
+	csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
 	end
 end
 assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
@@ -8358,15 +8384,15 @@
 end
 assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
@@ -8449,15 +8475,15 @@
 end
 assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+	csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+	csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
 	end
 end
 assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
@@ -8488,15 +8514,15 @@
 end
 assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
 always @(*) begin
-	csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+	csrbank2_dfii_pi1_rddata0_re <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+		csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+	csrbank2_dfii_pi1_rddata0_we <= 1'd0;
 	if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+		csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
 	end
 end
 assign litedramcore_sel = litedramcore_storage[0];
@@ -11194,6 +11220,17 @@
 	litedramcore_new_master_rdata_valid11 <= litedramcore_new_master_rdata_valid10;
 	litedramcore_new_master_rdata_valid12 <= litedramcore_new_master_rdata_valid11;
 	litedramcore_new_master_rdata_valid13 <= litedramcore_new_master_rdata_valid12;
+	if (wb_port_ack) begin
+		cmd_consumed <= 1'd0;
+		wdata_consumed <= 1'd0;
+	end else begin
+		if ((user_port_cmd_valid & user_port_cmd_ready)) begin
+			cmd_consumed <= 1'd1;
+		end
+		if ((user_port_wdata_valid & user_port_wdata_ready)) begin
+			wdata_consumed <= 1'd1;
+		end
+	end
 	state <= next_state;
 	if (litedramcore_dat_w_next_value_ce0) begin
 		litedramcore_dat_w <= litedramcore_dat_w_next_value0;
@@ -11626,6 +11663,8 @@
 		init_error_storage <= 1'd0;
 		init_error_re <= 1'd0;
 		user_enable <= 1'd0;
+		cmd_consumed <= 1'd0;
+		wdata_consumed <= 1'd0;
 		litedramcore_refresher_state <= 2'd0;
 		litedramcore_bankmachine0_state <= 3'd0;
 		litedramcore_bankmachine1_state <= 3'd0;
@@ -13409,5 +13448,5 @@
 endmodule
 
 // -----------------------------------------------------------------------------
-//  Auto-Generated by LiteX on 2023-05-07 21:36:35.
+//  Auto-Generated by LiteX on 2023-04-24 22:46:16.
 //------------------------------------------------------------------------------