From 5fe431f3e515e6a85150fc6fd6f61d610478c0b5 Mon Sep 17 00:00:00 2001
From: Emin Fedar <eminfedar@gmail.com>
Date: Sun, 23 May 2021 15:00:16 +0300
Subject: [PATCH] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 0acc943..a69348d 100644
--- a/README.md
+++ b/README.md
@@ -3,7 +3,7 @@
 
 Fedar F1 is a 5-Stage Pipelined (Fetch|Decode|Execute|Memory|Writeback) RV64IM RISC-V Core written fully in Verilog.
 
-![Simulated GTKWave output of the CPU](https://raw.githubusercontent.com/eminfedar/rv64im-verilog/main/gtkwave-image.png)
+![Simulated GTKWave output of the CPU](https://raw.githubusercontent.com/eminfedar/fedar-f1-rv64im/main/gtkwave-image.png)
 
 ## How to compile?