This is a project for our Computer Architecture and Organization course, under the professor Nestor Rodríguez.
The project consists of designing and simulating an architecture that is compliant with SPARC V8. We will only be implementing the Integer Unit(IU) Instructions.
Some of the components designed include:
- Control Unit
- ALU
- RAM
- Register File with Register Windows
- Auxiliary modules such as Muxes and Decoders
Tools utilized:
- Verilog
- iverilog compiler with vvp
- ModelSim
- SublimeText Editor
Contributors:
- Rafael Pol
- Edwin Badillo
- Carlos N. Abreu Takemura