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lbednarz
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merged RX stuff
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@6831 35acf78f-673a-0410-8e92-d51de3d6d3f4
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‎boards/RENESAS_RPBRX62N/board.c

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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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const PALConfig pal_default_config = {
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{VAL_PORT0DATA, VAL_PORT0DIR, VAL_PORT0ICR, VAL_PORT0ODR, 0},
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{VAL_PORT1DATA, VAL_PORT1DIR, VAL_PORT1ICR, VAL_PORT1ODR, 0},
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{VAL_PORT2DATA, VAL_PORT2DIR, VAL_PORT2ICR, VAL_PORT2ODR, 0},
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{VAL_PORT3DATA, VAL_PORT3DIR, VAL_PORT3ICR, VAL_PORT3ODR, 0},
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{VAL_PORT4DATA, VAL_PORT4DIR, VAL_PORT4ICR, 0 , 0},
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{VAL_PORT5DATA, VAL_PORT5DIR, VAL_PORT5ICR, 0 , 0},
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{VAL_PORTADATA, VAL_PORTADIR, VAL_PORTAICR, 0 , VAL_PORTAPCR},
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{VAL_PORTBDATA, VAL_PORTBDIR, VAL_PORTBICR, 0 , VAL_PORTBPCR},
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{VAL_PORTCDATA, VAL_PORTCDIR, VAL_PORTCICR, VAL_PORTCODR, VAL_PORTCPCR},
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{VAL_PORTDDATA, VAL_PORTDDIR, VAL_PORTDICR, 0 , VAL_PORTDPCR},
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{VAL_PORTEDATA, VAL_PORTEDIR, VAL_PORTEICR, 0 , VAL_PORTEPCR},
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};
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#endif
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/**
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* @brief CMT3 interrupt handler.
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*/
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CH_IRQ_HANDLER(Excep_CMTU1_CMT3) {
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CH_IRQ_PROLOGUE();
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chSysLockFromIsr();
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chSysTimerHandlerI();
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chSysUnlockFromIsr();
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CH_IRQ_EPILOGUE();
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}
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/*
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* Early initialization code.
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* This initialization must be performed just after stack setup and before
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* any other initialization.
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*/
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void __early_init(void) {
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rx62n_clock_init();
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}
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/*
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* Board-specific initialization code.
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*/
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void boardInit(void) {
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/* Setup tick timer */
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MSTP(CMT3) = 0; /* Enable CMT3 timer (cancel module stop state) */
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CMT.CMSTR1.BIT.STR3 = 0; /* Stop timer */
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CMT3.CMCR.BIT.CKS = 2; /* PCLK/128 */
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CMT3.CMCNT = 0;
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CMT3.CMCOR = RX62N_PERCLK / 128 / CH_FREQUENCY;
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CMT3.CMCR.BIT.CMIE = 1; /* Enable compare match interrupts */
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IEN(CMT3,CMI3) = 1; /* Set Interrupt Enable Register */
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IPR(CMT3,CMI3) = 8; /* Setup interrupt priority */
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CMT.CMSTR1.BIT.STR3 = 1; /* Start timer */
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}

‎boards/RENESAS_RPBRX62N/board.h

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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Setup for Renesas RPBRX62N board
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*/
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/*
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* Board identifiers.
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*/
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#define BOARD_RPBRX62N
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#define BOARD_NAME "Renesas RPBRX62N"
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/*
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* Board frequencies.
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*/
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#define EXTALCLK 12000000
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#define SUBCLK 32768
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/*
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* MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
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*/
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#define RX62NXBDFP
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/* TODO: move this to hal/include/mii.h */
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#define MII_LAN8700_ID 0x0007C0C4
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/*
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* Ethernet PHY type.
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*/
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#define BOARD_PHY_ID MII_LAN8700_ID
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/*
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* Ethernet PHY address.
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*/
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#define BOARD_PHY_ADDRESS 31
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#define RX62N_MAC_PHY_TIMEOUT 0
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/*
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* Use ethernet PHY RMII interface (if defined).
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*/
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/*#define BOARD_PHY_RMII*/
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/*
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* Ethernet PHY hardware reset
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* PORTA_ETH_RESETOUT must be held low for at least 100us.
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*/
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#define BOARD_PHY_RESET() do { \
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palClearPad(GPIO10, PORTA_ETH_RESETOUT); \
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asm volatile ("mov.l #2640,r2 \n\t" \
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"1: \n\t" \
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"sub #1,r2 \n\t" \
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"bne.b 1b \n\t"); \
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palSetPad(GPIO10, PORTA_ETH_RESETOUT); \
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} while(0)
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/*
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* PORT 0 initial setup.
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*/
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#define VAL_PORT0DIR 0x00
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#define VAL_PORT0DATA 0x00
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#define VAL_PORT0ICR 0x00
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#define VAL_PORT0ODR 0x00
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/*
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* PORT 1 initial setup.
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*/
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#define VAL_PORT1DIR 0x00
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#define VAL_PORT1DATA 0x00
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#define VAL_PORT1ICR 0x00
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#define VAL_PORT1ODR 0x00
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/*
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* PORT 2 initial setup.
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*/
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#define VAL_PORT2DIR 0x00
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#define VAL_PORT2DATA 0x00
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#define VAL_PORT2ICR 0x00
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#define VAL_PORT2ODR 0x00
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/*
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* PORT 3 initial setup.
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*/
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#define VAL_PORT3DIR 0x00
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#define VAL_PORT3DATA 0x00
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#define VAL_PORT3ICR 0x00
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#define VAL_PORT3ODR 0x00
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/*
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* PORT 4 initial setup.
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*/
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#define VAL_PORT4DIR 0x00
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#define VAL_PORT4DATA 0x00
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#define VAL_PORT4ICR 0x00
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/*
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* PORT 5 initial setup.
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*/
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#define VAL_PORT5DIR 0x00
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#define VAL_PORT5DATA 0x00
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#define VAL_PORT5ICR 0x00
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/*
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* GPIO A initial setup.
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*/
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#define VAL_PORTADIR PAL_PORT_BIT(PORTA_LED0) | \
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PAL_PORT_BIT(PORTA_LED1) | \
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PAL_PORT_BIT(PORTA_LED2) | \
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PAL_PORT_BIT(PORTA_MII_MDIO) | \
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PAL_PORT_BIT(PORTA_MII_MDC) | \
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PAL_PORT_BIT(PORTA_ETH_LINKSTA) | \
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PAL_PORT_BIT(PORTA_ETH_RESETOUT)
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#define VAL_PORTADATA PAL_PORT_BIT(PORTA_LED0) | \
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PAL_PORT_BIT(PORTA_LED1) | \
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PAL_PORT_BIT(PORTA_LED2) | \
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PAL_PORT_BIT(PORTA_ETH_RESETOUT)
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#define VAL_PORTAICR PAL_PORT_BIT(PORTA_MII_MDIO) | \
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PAL_PORT_BIT(PORTA_ETH_LINKSTA)
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#define VAL_PORTAPCR 0x00
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/*
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* PORT B initial setup.
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*/
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#define VAL_PORTBDIR PAL_PORT_BIT(PORTB_MII_TXD1) | \
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PAL_PORT_BIT(PORTB_MII_TXD0) | \
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PAL_PORT_BIT(PORTB_MII_TXEN)
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#define VAL_PORTBDATA 0x00
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#define VAL_PORTBICR PAL_PORT_BIT(PORTB_MII_CRS) | \
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PAL_PORT_BIT(PORTB_MII_RXER) | \
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PAL_PORT_BIT(PORTB_MII_RXCLK) | \
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PAL_PORT_BIT(PORTB_MII_RXD0) | \
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PAL_PORT_BIT(PORTB_MII_RXD1)
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#define VAL_PORTBPCR 0x00
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/*
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* PORT C initial setup.
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*/
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#define VAL_PORTCDIR PAL_PORT_BIT(PORTC_MII_TXD3) | \
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PAL_PORT_BIT(PORTC_MII_TXD2) | \
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PAL_PORT_BIT(PORTC_MII_TXER)
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#define VAL_PORTCDATA 0x00
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#define VAL_PORTCICR PAL_PORT_BIT(PORTC_MII_COL) | \
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PAL_PORT_BIT(PORTC_MII_TXCLK) | \
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PAL_PORT_BIT(PORTC_MII_TXER) | \
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PAL_PORT_BIT(PORTC_MII_RXDV) | \
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PAL_PORT_BIT(PORTC_MII_RXD2) | \
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PAL_PORT_BIT(PORTC_MII_RXD3)
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#define VAL_PORTCODR 0x00
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#define VAL_PORTCPCR 0x00
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/*
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* PORT D initial setup.
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*/
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#define VAL_PORTDDIR 0x00
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#define VAL_PORTDDATA 0x00
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#define VAL_PORTDICR 0x00
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#define VAL_PORTDPCR 0x00
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/*
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* PORT E initial setup.
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*/
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#define VAL_PORTEDIR 0x00
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#define VAL_PORTEDATA 0x00
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#define VAL_PORTEICR 0x00
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#define VAL_PORTEPCR 0x00
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/*
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* Pin definitions.
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*/
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#define PORTA_ETH_RESETOUT 7
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#define PORTA_ETH_LINKSTA 5
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#define PORTA_MII_MDC 4
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#define PORTA_MII_MDIO 3
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#define PORTA_LED0 2
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#define PORTA_LED1 1
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#define PORTA_LED2 0
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#define PORTB_MII_CRS 7
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#define PORTB_MII_TXD1 6
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#define PORTB_MII_TXD0 5
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#define PORTB_MII_TXEN 4
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#define PORTB_MII_RXER 3
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#define PORTB_MII_RXCLK 2
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#define PORTB_MII_RXD0 1
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#define PORTB_MII_RXD1 0
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#define PORTC_MII_COL 7
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#define PORTC_MII_TXD3 6
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#define PORTC_MII_TXD2 5
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#define PORTC_MII_TXCLK 4
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#define PORTC_MII_TXER 3
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#define PORTC_MII_RXDV 2
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#define PORTC_MII_RXD2 1
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#define PORTC_MII_RXD3 0
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#if !defined(_FROM_ASM_)
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#ifdef __cplusplus
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extern "C" {
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#endif
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void boardInit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _FROM_ASM_ */
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#endif /* _BOARD_H_ */

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/!prog.bat

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@echo off
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set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
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jlink.exe r5f562n8bdfp_ram_wr.script

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/!rd.bat

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@echo off
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set path=c:\Program Files (x86)\SEGGER\JLinkARM_V442a
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jlink.exe r5f562n8bdfp_rd.script

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/!rst.bat

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@echo off
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set path=c:\Program Files (x86)\SEGGER\JLinkARM_V432b
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jlink.exe reset.script

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/lss.bat

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@echo off
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set path="d:\Program Files\KPIT\GNURX\rx-elf\rx-elf\bin"
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rx-elf-objdump -h -S rx62n_demo.exe >rx62n_demo.lss

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/r5f562n8bdfp_ram_wr.script

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exec device = RX62N
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speed auto
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loadbin rx62n_demo.bin, 0x00000000
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r
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g
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q

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/r5f562n8bdfp_rd.script

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exec device = RX62N
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speed auto
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savebin ram_dump.bin, 0x00000000, 0x18000
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r
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g
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q

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/reset.script

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exec device = RX62N
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speed auto
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r
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g
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q

‎demos/RX-RX62N-RPB-MAC/bin/Release_ram/rx62n_demo_vectors_0xFFFFFF80.bin

128 Bytes
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