From f7bab9a00fabad4b99676f9c7bd0b6e8e918a4a6 Mon Sep 17 00:00:00 2001
From: Sanghyeon Lee <smartleesh@outlook.com>
Date: Tue, 2 Dec 2025 04:48:33 +0900
Subject: [PATCH 1/2] [RISC-V] Enhance the utilization of shXadd instructions *
 Prevent the addressing mode nodes(GT_CAST, GT_LSH and GT_MUL) being moved by
 the CSE in RISCV64.

* Previously the nodes [GT_CAST + GT_LSH(or MUL) + GT_ADD] were lowered into [slli(.uw) + add]. Now it is emitted with a single shXadd(.uw).
---
 src/coreclr/jit/emitriscv64.cpp |  2 +-
 src/coreclr/jit/gentree.cpp     | 34 ++++++++++++++++++++++++++++++++-
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/src/coreclr/jit/emitriscv64.cpp b/src/coreclr/jit/emitriscv64.cpp
index 653c48536b0071..38731cf0ca0b93 100644
--- a/src/coreclr/jit/emitriscv64.cpp
+++ b/src/coreclr/jit/emitriscv64.cpp
@@ -4488,7 +4488,7 @@ void emitter::emitDispFrameRef(int varx, int disp, int offs, bool asmfm)
 #endif // DEBUG
 
 // Generate code for a load or store operation with a potentially complex addressing mode
-// This method handles the case of a GT_IND with contained GT_LEA op1 of the x86 form [base + index*sccale + offset]
+// This method handles the case of a GT_IND with contained GT_LEA op1 of the x86 form [base + index*scale + offset]
 //
 void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataReg, GenTreeIndir* indir)
 {
diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
index eb6f6ad1fb2876..e13d3f942a7adc 100644
--- a/src/coreclr/jit/gentree.cpp
+++ b/src/coreclr/jit/gentree.cpp
@@ -4809,9 +4809,41 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ
         gtWalkOp(&op2, &op1, nullptr, true);
 #endif // defined(TARGET_XARCH)
 
-        if ((mul > 1) && (op2 != nullptr) && op2->OperIs(GT_LSH, GT_MUL))
+        bool noCSE = (mul > 1);
+#if defined(TARGET_RISCV64) // namu
+        noCSE = this->compOpportunisticallyDependsOn(InstructionSet_Zba);
+#endif
+
+        if (noCSE && (op2 != nullptr) && op2->OperIs(GT_LSH, GT_MUL))
         {
             op2->gtFlags |= GTF_ADDRMODE_NO_CSE;
+
+#if defined(TARGET_RISCV64) // namu
+            // RISC-V addressing mode is based on: (base + index*scale) + offset.
+            // To emit shXadd.uw, GT_ADD + GT_LSH(or MUL) + GT_CAST nodes are required.
+            // GT_CAST nodes benefit from shXadd.uw variants(Zba) by disabling CSEs.
+            //
+            // Example:
+            //      ADD
+            //      |- ADD
+            //      |  |- LCL_VAR       (base)
+            //      |  |- LSH (or MUL)  (index * scale)
+            //      |     |- GT_CAST    (index, CSE shouldn't be applied on this node to emit shXadd.uw)
+            //      |        |- OP1     (CSE/ConstCSE possible on this node and its children)
+            //      |     |- CNS_INT    (scale)
+            //      |- CNS_INT          (offset)
+            //
+            // Other nodes than GT_CAST can benefit from shXadd variants without GTF_DONT_CSE flags,
+            // because shXadd doesn't require a GT_CAST node.
+
+            GenTree* index = op2->gtGetOp1();
+            if ((index != nullptr) && index->OperIs(GT_CAST))
+            {
+                assert(index->TypeIs(TYP_I_IMPL));
+                index->gtFlags |= GTF_DONT_CSE;
+            }
+
+#endif
         }
 
         // Finally, adjust the costs on the parenting COMMAs.

From fd17a4a63b45c008c53dffd77a7fab970bd9e3ee Mon Sep 17 00:00:00 2001
From: Sanghyeon Lee <sanghyeon@snu.ac.kr>
Date: Tue, 2 Dec 2025 10:37:58 +0900
Subject: [PATCH 2/2] cleanup

---
 src/coreclr/jit/gentree.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/coreclr/jit/gentree.cpp b/src/coreclr/jit/gentree.cpp
index e13d3f942a7adc..15e88fa4864b8f 100644
--- a/src/coreclr/jit/gentree.cpp
+++ b/src/coreclr/jit/gentree.cpp
@@ -4810,7 +4810,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ
 #endif // defined(TARGET_XARCH)
 
         bool noCSE = (mul > 1);
-#if defined(TARGET_RISCV64) // namu
+#if defined(TARGET_RISCV64)
         noCSE = this->compOpportunisticallyDependsOn(InstructionSet_Zba);
 #endif
 
@@ -4818,7 +4818,7 @@ bool Compiler::gtMarkAddrMode(GenTree* addr, int* pCostEx, int* pCostSz, var_typ
         {
             op2->gtFlags |= GTF_ADDRMODE_NO_CSE;
 
-#if defined(TARGET_RISCV64) // namu
+#if defined(TARGET_RISCV64)
             // RISC-V addressing mode is based on: (base + index*scale) + offset.
             // To emit shXadd.uw, GT_ADD + GT_LSH(or MUL) + GT_CAST nodes are required.
             // GT_CAST nodes benefit from shXadd.uw variants(Zba) by disabling CSEs.