diff --git a/src/coreclr/jit/compiler.h b/src/coreclr/jit/compiler.h
index abd9666e5114bf..f0ac25b8d0b20e 100644
--- a/src/coreclr/jit/compiler.h
+++ b/src/coreclr/jit/compiler.h
@@ -9385,6 +9385,13 @@ class Compiler
             simdType = TYP_SIMD64;
         }
 #endif // TARGET_XARCH
+#if defined(TARGET_ARM64)
+        else if (size == SIZE_UNKNOWN)
+        {
+            assert(JitConfig.JitUseScalableVectorT());
+            simdType = TYP_SIMD;
+        }
+#endif
         else
         {
             noway_assert(!"Unexpected size for SIMD type");
diff --git a/src/coreclr/jit/importer.cpp b/src/coreclr/jit/importer.cpp
index e9e4bc20ee5931..63da7f19ad610d 100644
--- a/src/coreclr/jit/importer.cpp
+++ b/src/coreclr/jit/importer.cpp
@@ -1189,7 +1189,7 @@ var_types Compiler::impNormStructType(CORINFO_CLASS_HANDLE structHnd, var_types*
             var_types    simdBaseType = getBaseTypeAndSizeOfSIMDType(structHnd, &sizeBytes);
             if (simdBaseType != TYP_UNDEF)
             {
-                assert(sizeBytes == originalSize);
+                assert(sizeBytes == originalSize || sizeBytes == SIZE_UNKNOWN);
                 structType = getSIMDTypeForSize(sizeBytes);
                 if (pSimdBaseJitType != nullptr)
                 {
diff --git a/src/coreclr/jit/jitconfigvalues.h b/src/coreclr/jit/jitconfigvalues.h
index 3a9188a3e1eb0f..af4f3baca368f6 100644
--- a/src/coreclr/jit/jitconfigvalues.h
+++ b/src/coreclr/jit/jitconfigvalues.h
@@ -844,6 +844,9 @@ CONFIG_STRING(JitRawHexCodeFile, "JitRawHexCodeFile")
 //    3: force all frames to use the frame types that save FP/LR registers with the callee-saved registers (at the top
 //    of the frame) and also force using the large funclet frame variation (frame 5) if possible.
 CONFIG_INTEGER(JitSaveFpLrWithCalleeSavedRegisters, "JitSaveFpLrWithCalleeSavedRegisters", 0)
+
+// Experimental support for vector length agnostic implementation of Vector<T>
+CONFIG_INTEGER(JitUseScalableVectorT, "JitUseScalableVectorT", 0)
 #endif // defined(TARGET_ARM64)
 
 #if defined(TARGET_LOONGARCH64)
diff --git a/src/coreclr/jit/simd.cpp b/src/coreclr/jit/simd.cpp
index d818285410c919..66a65af1403865 100644
--- a/src/coreclr/jit/simd.cpp
+++ b/src/coreclr/jit/simd.cpp
@@ -628,6 +628,15 @@ CorInfoType Compiler::getBaseJitTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeH
                         }
 
                         JITDUMP(" Found Vector<%s>\n", varTypeName(JitType2PreciseVarType(simdBaseJitType)));
+
+#if defined(DEBUG) && defined(TARGET_ARM64)
+                        if (JitConfig.JitUseScalableVectorT() &&
+                            compOpportunisticallyDependsOn(InstructionSet_Sve_Arm64))
+                        {
+                            size = SIZE_UNKNOWN;
+                            break;
+                        }
+#endif
                         size = getVectorTByteLength();
 
                         if (size == 0)
@@ -765,7 +774,7 @@ CorInfoType Compiler::getBaseJitTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeH
 
     if (simdBaseJitType != CORINFO_TYPE_UNDEF)
     {
-        assert(size == info.compCompHnd->getClassSize(typeHnd));
+        assert(size == info.compCompHnd->getClassSize(typeHnd) || size == SIZE_UNKNOWN);
         setUsesSIMDTypes(true);
     }
 
diff --git a/src/coreclr/jit/simd.h b/src/coreclr/jit/simd.h
index 159f626eefa8de..78553b131be3dc 100644
--- a/src/coreclr/jit/simd.h
+++ b/src/coreclr/jit/simd.h
@@ -4,6 +4,8 @@
 #ifndef _SIMD_H_
 #define _SIMD_H_
 
+#define SIZE_UNKNOWN UINT8_MAX
+
 template <typename T>
 static bool ElementsAreSame(T* array, size_t size)
 {
diff --git a/src/coreclr/jit/typelist.h b/src/coreclr/jit/typelist.h
index 865c177bc7bc32..b2cf2ffa1390f4 100644
--- a/src/coreclr/jit/typelist.h
+++ b/src/coreclr/jit/typelist.h
@@ -4,6 +4,8 @@
 #define GCS EA_GCREF
 #define BRS EA_BYREF
 #define EPS EA_PTRSIZE
+#define EAU EA_UNKNOWN
+#define SZU SIZE_UNKNOWN
 #define PS  TARGET_POINTER_SIZE
 #define PST (TARGET_POINTER_SIZE / sizeof(int))
 
@@ -63,6 +65,8 @@ DEF_TP(SIMD16   ,"simd16" , TYP_SIMD16,  16,16, 16,   4,16, VTR_FLOAT, available
 #if defined(TARGET_XARCH)
 DEF_TP(SIMD32   ,"simd32" , TYP_SIMD32,  32,32, 32,   8,16, VTR_FLOAT, availableDoubleRegs, RBM_FLT_CALLEE_SAVED,    RBM_FLT_CALLEE_TRASH,    VTF_S|VTF_VEC)
 DEF_TP(SIMD64   ,"simd64" , TYP_SIMD64,  64,64, 64,  16,16, VTR_FLOAT, availableDoubleRegs, RBM_FLT_CALLEE_SAVED,    RBM_FLT_CALLEE_TRASH,    VTF_S|VTF_VEC)
+#elif defined(TARGET_ARM64)
+DEF_TP(SIMD     ,"simd" ,   TYP_SIMD,   SZU,EAU,EAU,  0,16, VTR_FLOAT, availableDoubleRegs, RBM_FLT_CALLEE_SAVED,    RBM_FLT_CALLEE_TRASH,    VTF_S|VTF_VEC)
 #endif // TARGET_XARCH
 #if defined(FEATURE_MASKED_HW_INTRINSICS)
 DEF_TP(MASK     ,"mask"   , TYP_MASK,     8, 8,  8,   2, 8, VTR_MASK,  availableMaskRegs,   RBM_MSK_CALLEE_SAVED,    RBM_MSK_CALLEE_TRASH,    VTF_S)