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[RISC-V] Substituting INS_ori and INS_addi with INS_mov for zero immediate values #116956

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Merged
merged 5 commits into from
Jun 30, 2025
Merged

[RISC-V] Substituting INS_ori and INS_addi with INS_mov for zero immediate values #116956

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d536d3c
[RISC-V] Replace INS_ori with INS_mov when immediate is 0
namu-lee Jun 24, 2025
735cdcd
[RISC-V] Replace INS_addi with INS_mov when immediate is 0
namu-lee Jun 24, 2025
fae8f21
Improve code style
namu-lee Jun 25, 2025
10a76f3
Substitute INS_slliw with INS_sext_w when immediate is 0
namu-lee Jun 25, 2025
92cc1f5
Merge branch 'main' into instruction-compression
namu-lee Jun 26, 2025
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20 changes: 10 additions & 10 deletions src/coreclr/jit/codegenriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1344,7 +1344,7 @@ void CodeGen::genSimpleReturn(GenTree* treeNode)
}
else
{
GetEmitter()->emitIns_R_R_I(attr == EA_4BYTE ? INS_addiw : INS_addi, attr, retReg, op1->GetRegNum(), 0);
GetEmitter()->emitIns_R_R(attr == EA_4BYTE ? INS_sext_w : INS_mov, attr, retReg, op1->GetRegNum());
}
}
}
Expand Down Expand Up @@ -1418,7 +1418,7 @@ void CodeGen::genLclHeap(GenTree* tree)
regCnt = internalRegisters.Extract(tree);
if (regCnt != targetReg)
{
emit->emitIns_R_R_I(INS_ori, easz, regCnt, targetReg, 0);
emit->emitIns_R_R(INS_mov, easz, regCnt, targetReg);
}
}

Expand Down Expand Up @@ -1592,15 +1592,15 @@ void CodeGen::genLclHeap(GenTree* tree)

// Overflow, set regCnt to lowest possible value
emit->emitIns_R_R_I(INS_beq, EA_PTRSIZE, tempReg, REG_R0, 2 << 2);
emit->emitIns_R_R_I(INS_addi, EA_PTRSIZE, regCnt, REG_R0, 0);
emit->emitIns_R_R(INS_mov, EA_PTRSIZE, regCnt, REG_R0);

regNumber rPageSize = internalRegisters.GetSingle(tree);

noway_assert(rPageSize != tempReg);

emit->emitIns_R_I(INS_lui, EA_PTRSIZE, rPageSize, pageSize >> 12);
regSet.verifyRegUsed(rPageSize);
emit->emitIns_R_R_I(INS_addi, EA_PTRSIZE, tempReg, REG_SPBASE, 0);
emit->emitIns_R_R(INS_mov, EA_PTRSIZE, tempReg, REG_SPBASE);

// tickle the page - this triggers a page fault when on the guard page
emit->emitIns_R_R_I(INS_lw, EA_4BYTE, REG_R0, tempReg, 0);
Expand All @@ -1611,7 +1611,7 @@ void CodeGen::genLclHeap(GenTree* tree)
// lastTouchDelta is dynamic, and can be up to a page. So if we have outgoing arg space,
// we're going to assume the worst and probe.
// Move the final value to SP
emit->emitIns_R_R_I(INS_addi, EA_PTRSIZE, REG_SPBASE, regCnt, 0);
emit->emitIns_R_R(INS_mov, EA_PTRSIZE, REG_SPBASE, regCnt);
}

ALLOC_DONE:
Expand Down Expand Up @@ -1639,7 +1639,7 @@ void CodeGen::genLclHeap(GenTree* tree)
else // stackAdjustment == 0
{
// Move the final value of SP to targetReg
emit->emitIns_R_R_I(INS_ori, EA_PTRSIZE, targetReg, REG_SPBASE, 0);
emit->emitIns_R_R(INS_mov, EA_PTRSIZE, targetReg, REG_SPBASE);
}

BAILOUT:
Expand Down Expand Up @@ -6044,18 +6044,18 @@ void CodeGen::genIntToIntCast(GenTreeCast* cast)
}
break;
case GenIntCastDesc::SIGN_EXTEND_INT:
emit->emitIns_R_R_I(INS_slliw, EA_4BYTE, dstReg, srcReg, 0);
emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dstReg, srcReg);
break;

default:
assert(desc.ExtendKind() == GenIntCastDesc::COPY);
if (srcType == TYP_INT)
{
emit->emitIns_R_R_I(INS_slliw, EA_4BYTE, dstReg, srcReg, 0);
emit->emitIns_R_R(INS_sext_w, EA_4BYTE, dstReg, srcReg);
}
else
{
emit->emitIns_R_R_I(INS_addi, EA_PTRSIZE, dstReg, srcReg, 0);
emit->emitIns_R_R(INS_mov, EA_PTRSIZE, dstReg, srcReg);
}
break;
}
Expand Down Expand Up @@ -6300,7 +6300,7 @@ void CodeGen::genLeaInstruction(GenTreeAddrMode* lea)
{
if (lea->GetRegNum() != memBase->GetRegNum())
{
emit->emitIns_R_R_I(INS_ori, size, lea->GetRegNum(), memBase->GetRegNum(), 0);
emit->emitIns_R_R(INS_mov, size, lea->GetRegNum(), memBase->GetRegNum());
}
}
}
Expand Down
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