diff --git a/src/coreclr/jit/hwintrinsic.h b/src/coreclr/jit/hwintrinsic.h index a0259f32ac0972..0575ec47dd1a1a 100644 --- a/src/coreclr/jit/hwintrinsic.h +++ b/src/coreclr/jit/hwintrinsic.h @@ -1159,12 +1159,16 @@ struct HWIntrinsicInfo { case NI_Sve_And: return NI_Sve_And_Predicates; + case NI_Sve_AndNot: + return NI_Sve_AndNot_Predicates; case NI_Sve_BitwiseClear: return NI_Sve_BitwiseClear_Predicates; case NI_Sve_Xor: return NI_Sve_Xor_Predicates; case NI_Sve_Or: return NI_Sve_Or_Predicates; + case NI_Sve_OrNot: + return NI_Sve_OrNot_Predicates; case NI_Sve_ZipHigh: return NI_Sve_ZipHigh_Predicates; case NI_Sve_ZipLow: diff --git a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp index e83fb55e1a18c5..782db25a6d0331 100644 --- a/src/coreclr/jit/hwintrinsiccodegenarm64.cpp +++ b/src/coreclr/jit/hwintrinsiccodegenarm64.cpp @@ -702,9 +702,25 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node) break; } + case NI_Sve_AndNot: + // Emit an unpredicated AND (to avoid the RMW constraints), then a predicated NOT + GetEmitter()->emitIns_R_R_R(INS_sve_and, emitSize, targetReg, embMaskOp1Reg, + embMaskOp2Reg, opt); + GetEmitter()->emitIns_R_R_R(INS_sve_not, emitSize, targetReg, maskReg, targetReg, opt); + break; + + case NI_Sve_OrNot: + // Emit an unpredicated OR (to avoid the RMW constraints), then a predicated NOT + GetEmitter()->emitIns_R_R_R(INS_sve_orr, emitSize, targetReg, embMaskOp1Reg, + embMaskOp2Reg, opt); + GetEmitter()->emitIns_R_R_R(INS_sve_not, emitSize, targetReg, maskReg, targetReg, opt); + break; + case NI_Sve_And_Predicates: + case NI_Sve_AndNot_Predicates: case NI_Sve_BitwiseClear_Predicates: case NI_Sve_Or_Predicates: + case NI_Sve_OrNot_Predicates: case NI_Sve_Xor_Predicates: GetEmitter()->emitIns_R_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg, embMaskOp2Reg, INS_OPTS_SCALABLE_B); diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h index 47c73db897ad9e..a6f842bf22e94e 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64sve.h +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -29,6 +29,7 @@ HARDWARE_INTRINSIC(Sve, AddSaturate, HARDWARE_INTRINSIC(Sve, AddSequentialAcross, -1, -1, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_fadda, INS_sve_fadda}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_ReduceOperation) HARDWARE_INTRINSIC(Sve, And, -1, -1, {INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_HasAllMaskVariant) HARDWARE_INTRINSIC(Sve, AndAcross, -1, -1, {INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_sve_andv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_ReduceOperation) +HARDWARE_INTRINSIC(Sve, AndNot, -1, -1, {INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_ZeroingMaskedOperation|HW_Flag_HasAllMaskVariant) HARDWARE_INTRINSIC(Sve, BitwiseClear, -1, -1, {INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_HasAllMaskVariant) HARDWARE_INTRINSIC(Sve, BooleanNot, -1, -1, {INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_sve_cnot, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, Compact, -1, 2, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_compact, INS_sve_compact, INS_sve_compact, INS_sve_compact, INS_sve_compact, INS_sve_compact}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation) @@ -230,6 +231,7 @@ HARDWARE_INTRINSIC(Sve, Negate, HARDWARE_INTRINSIC(Sve, Not, -1, -1, {INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_sve_not, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation) HARDWARE_INTRINSIC(Sve, Or, -1, -1, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_OptionalEmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation|HW_Flag_HasAllMaskVariant) HARDWARE_INTRINSIC(Sve, OrAcross, -1, -1, {INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_sve_orv, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_ReduceOperation) +HARDWARE_INTRINSIC(Sve, OrNot, -1, -1, {INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_ZeroingMaskedOperation|HW_Flag_HasAllMaskVariant) HARDWARE_INTRINSIC(Sve, PopCount, -1, -1, {INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt, INS_sve_cnt}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_BaseTypeFromFirstArg|HW_Flag_EmbeddedMaskedOperation|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve, Prefetch16Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_sve_prfh, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) HARDWARE_INTRINSIC(Sve, Prefetch32Bit, -1, 3, {INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_invalid, INS_sve_prfw, INS_invalid, INS_invalid, INS_invalid, INS_invalid}, HW_Category_Special, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_BaseTypeFromFirstArg|HW_Flag_HasImmediateOperand|HW_Flag_SpecialSideEffect_Other) @@ -353,8 +355,10 @@ HARDWARE_INTRINSIC(Sve, StoreAndZipx3, HARDWARE_INTRINSIC(Sve, StoreAndZipx4, -1, 3, {INS_sve_st4b, INS_sve_st4b, INS_sve_st4h, INS_sve_st4h, INS_sve_st4w, INS_sve_st4w, INS_sve_st4d, INS_sve_st4d, INS_sve_st4w, INS_sve_st4d}, HW_Category_MemoryStore, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_ExplicitMaskedOperation|HW_Flag_LowMaskedOperation|HW_Flag_NeedsConsecutiveRegisters) // Predicate variants of intrinsics, these are specialized for operating on TYP_MASK type values. HARDWARE_INTRINSIC(Sve, And_Predicates, -1, 2, {INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_sve_and, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_EmbeddedMaskedOperation|HW_Flag_SpecialCodeGen) +HARDWARE_INTRINSIC(Sve, AndNot_Predicates, -1, -1, {INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_sve_nand, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_EmbeddedMaskedOperation|HW_Flag_SpecialCodeGen|HW_Flag_ZeroingMaskedOperation) HARDWARE_INTRINSIC(Sve, BitwiseClear_Predicates, -1, 2, {INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_sve_bic, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_EmbeddedMaskedOperation|HW_Flag_SpecialCodeGen) HARDWARE_INTRINSIC(Sve, Or_Predicates, -1, 2, {INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_sve_orr, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_EmbeddedMaskedOperation|HW_Flag_SpecialCodeGen) +HARDWARE_INTRINSIC(Sve, OrNot_Predicates, -1, -1, {INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_sve_nor, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_EmbeddedMaskedOperation|HW_Flag_SpecialCodeGen|HW_Flag_ZeroingMaskedOperation) HARDWARE_INTRINSIC(Sve, Xor_Predicates, -1, 2, {INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_sve_eor, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_EmbeddedMaskedOperation|HW_Flag_SpecialCodeGen) HARDWARE_INTRINSIC(Sve, ConditionalSelect_Predicates, -1, 3, {INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel, INS_sve_sel}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask|HW_Flag_ExplicitMaskedOperation|HW_Flag_SpecialCodeGen) HARDWARE_INTRINSIC(Sve, ZipHigh_Predicates, -1, 2, {INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2, INS_sve_zip2}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_ReturnsPerElementMask) diff --git a/src/coreclr/jit/morph.cpp b/src/coreclr/jit/morph.cpp index 65f339748c0c22..9cc55d4fcd77aa 100644 --- a/src/coreclr/jit/morph.cpp +++ b/src/coreclr/jit/morph.cpp @@ -9805,16 +9805,20 @@ GenTree* Compiler::doMorphVectorOperandToMask(GenTree* node, GenTreeHWIntrinsic* // GenTreeHWIntrinsic* Compiler::fgMorphTryUseAllMaskVariant(GenTreeHWIntrinsic* node) { - if (HWIntrinsicInfo::HasAllMaskVariant(node->GetHWIntrinsicId())) + NamedIntrinsic intrinsicId = node->GetHWIntrinsicId(); + + if (HWIntrinsicInfo::HasAllMaskVariant(intrinsicId)) { - NamedIntrinsic maskVariant = HWIntrinsicInfo::GetMaskVariant(node->GetHWIntrinsicId()); + NamedIntrinsic maskVariant = HWIntrinsicInfo::GetMaskVariant(intrinsicId); // As some intrinsics have many variants, check that the count of operands on the node - // matches the number of operands required for the mask variant of the intrinsic. The mask - // variant of the intrinsic must have a fixed number of operands. - int numArgs = HWIntrinsicInfo::lookupNumArgs(maskVariant); - assert(numArgs >= 0); - if (node->GetOperandCount() == (size_t)numArgs) + // matches the number of operands required for the mask variant of the intrinsic. For + // embedded masks, the number of args are unknown. + int numArgs = HWIntrinsicInfo::lookupNumArgs(maskVariant); + bool embedded = HWIntrinsicInfo::IsEmbeddedMaskedOperation(maskVariant); + assert(numArgs >= 0 || embedded); + + if (node->GetOperandCount() == (size_t)numArgs || embedded) { // We're sure it will work at this point, so perform the pattern match on operands. if (canMorphAllVectorOperandsToMasks(node)) diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs index ae6363f0f40979..0b7a75dd4d79b9 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.PlatformNotSupported.cs @@ -581,6 +581,57 @@ internal Arm64() { } public static Vector AndAcross(Vector value) { throw new PlatformNotSupportedException(); } + // Bitwise NAND + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + // Bitwise clear /// @@ -7584,6 +7635,57 @@ internal Arm64() { } public static Vector OrAcross(Vector value) { throw new PlatformNotSupportedException(); } + // Bitwise NOR + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + // Count nonzero bits /// diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs index 25f5aed8441596..7c3514f461fafa 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve.cs @@ -578,6 +578,57 @@ internal Arm64() { } public static Vector AndAcross(Vector value) => AndAcross(value); + // Bitwise NAND + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + /// + /// svbool_t svnand[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NAND Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector AndNot(Vector left, Vector right) => AndNot(left, right); + + // Bitwise clear /// @@ -7575,6 +7626,57 @@ internal Arm64() { } public static Vector OrAcross(Vector value) => OrAcross(value); + // Bitwise NOR + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + /// + /// svbool_t svnor[_b]_z(svbool_t pg, svbool_t op1, svbool_t op2) + /// NOR Presult.B, Pg/Z, Pop1.B, Pop2.B + /// + public static Vector OrNot(Vector left, Vector right) => OrNot(left, right); + + // Count nonzero bits /// diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index 00c08ac75de140..fc793e3a1b5bfe 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -4582,6 +4582,14 @@ internal Arm64() { } public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector AndAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector AndNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector BitwiseClear(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector BitwiseClear(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector BitwiseClear(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } @@ -5591,6 +5599,14 @@ internal Arm64() { } public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector OrAcross(System.Numerics.Vector value) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector OrNot(System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector PopCount(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector PopCount(System.Numerics.Vector value) { throw null; } public static System.Numerics.Vector PopCount(System.Numerics.Vector value) { throw null; } diff --git a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs index 87f868fc04aa0e..6388488843f6e7 100644 --- a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs +++ b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs @@ -3199,6 +3199,15 @@ ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_AndAcross_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateReduceOpResult"] = "Helpers.AndAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_AndNot_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "AndNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.And(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_BitwiseClear_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "BitwiseClear", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(sbyte)TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "Helpers.BitwiseClear(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.BitwiseClear(left[i], right[i])"}), ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_BitwiseClear_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "BitwiseClear", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "(short)TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "Helpers.BitwiseClear(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.BitwiseClear(left[i], right[i])"}), ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_BitwiseClear_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "BitwiseClear", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "Helpers.BitwiseClear(left[i], right[i]) != result[i]", ["GetIterResult"] = "Helpers.BitwiseClear(left[i], right[i])"}), @@ -4204,6 +4213,15 @@ ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), ("SveVecReduceUnOpTest.template", new Dictionary { ["TestName"] = "Sve_OrAcross_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrAcross", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["ValidateReduceOpResult"] = "Helpers.OrAcross(firstOp) != result[0]", ["ValidateRemainingResults"] = "result[i] != 0"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_short", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_int", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_long", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_byte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_ushort", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_uint", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve_OrNot_ulong", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "OrNot", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["ValidateIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i])) != result[i]", ["GetIterResult"] = "Helpers.Not(Helpers.Or(left[i], right[i]))"}), + ("SveMasklessSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_PopCount_uint_float", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PopCount", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Single", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSingle()", ["ValidateIterResult"] = "(uint)Helpers.BitCount(firstOp[i]) != result[i]", ["GetIterResult"] = "(uint)Helpers.BitCount(leftOp[i])"}), ("SveMasklessSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_PopCount_ulong_double", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PopCount", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Double", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetDouble()", ["ValidateIterResult"] = "(ulong)Helpers.BitCount(firstOp[i]) != result[i]", ["GetIterResult"] = "(ulong)Helpers.BitCount(leftOp[i])"}), ("SveMasklessSimpleVecOpTest.template", new Dictionary { ["TestName"] = "Sve_PopCount_byte_sbyte", ["Isa"] = "Sve", ["LoadIsa"] = "Sve", ["Method"] = "PopCount", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["ValidateIterResult"] = "(byte)Helpers.BitCount(firstOp[i]) != result[i]", ["GetIterResult"] = "(byte)Helpers.BitCount(leftOp[i])"}), diff --git a/src/tests/JIT/opt/SVE/PredicateInstructions.cs b/src/tests/JIT/opt/SVE/PredicateInstructions.cs index 41b09c1fad3898..1e58d004424cb7 100644 --- a/src/tests/JIT/opt/SVE/PredicateInstructions.cs +++ b/src/tests/JIT/opt/SVE/PredicateInstructions.cs @@ -25,9 +25,11 @@ public static void TestPredicateInstructions() TransposeEven(); ReverseElement(); And(); + AndNot(); BitwiseClear(); Xor(); Or(); + OrNot(); ConditionalSelect(); } } @@ -92,6 +94,17 @@ static Vector And() ); } + [MethodImpl(MethodImplOptions.NoInlining)] + static Vector AndNot() + { + //ARM64-FULL-LINE: nand {{p[0-9]+}}.b, {{p[0-9]+}}/z, {{p[0-9]+}}.b, {{p[0-9]+}}.b + return Sve.ConditionalSelect( + Sve.CreateTrueMaskInt16(), + Sve.AndNot(Sve.CreateTrueMaskInt16(), Sve.CreateTrueMaskInt16()), + Vector.Zero + ); + } + [MethodImpl(MethodImplOptions.NoInlining)] static Vector BitwiseClear() { @@ -125,6 +138,17 @@ static Vector Or() ); } + [MethodImpl(MethodImplOptions.NoInlining)] + static Vector OrNot() + { + //ARM64-FULL-LINE: nor {{p[0-9]+}}.b, {{p[0-9]+}}/z, {{p[0-9]+}}.b, {{p[0-9]+}}.b + return Sve.ConditionalSelect( + Sve.CreateTrueMaskInt16(), + Sve.OrNot(Sve.CreateTrueMaskInt16(), Sve.CreateTrueMaskInt16()), + Vector.Zero + ); + } + [MethodImpl(MethodImplOptions.NoInlining)] static Vector ConditionalSelect() {