From 3e41e127a3cef818fc5a4e324422be69c409b126 Mon Sep 17 00:00:00 2001 From: Jonathan Davies Date: Wed, 11 Jun 2025 11:29:13 +0000 Subject: [PATCH 1/3] arm64: Add InterleavingXorEvenOdd & InterleavingXorOddEven * Implements #94020 --- src/coreclr/jit/hwintrinsiclistarm64sve.h | 2 + .../Arm/Sve2.PlatformNotSupported.cs | 116 ++++++++++++++++++ .../src/System/Runtime/Intrinsics/Arm/Sve2.cs | 98 +++++++++++++++ .../ref/System.Runtime.Intrinsics.cs | 16 +++ .../GenerateHWIntrinsicTests_Arm.cs | 17 +++ .../HardwareIntrinsics/Arm/Shared/Helpers.cs | 18 +++ 6 files changed, 267 insertions(+) diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h index 47c73db897ad9e..3da02ce85787bf 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64sve.h +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -322,6 +322,8 @@ HARDWARE_INTRINSIC(Sve2, BitwiseClearXor, HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, {INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, BitwiseSelectRightInverted, -1, 3, {INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) +HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics) +HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRounded, -1, -1, {INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRoundedSaturate, -1, -1, {INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticSaturate, -1, -1, {INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs index 3c3addb93aa4f0..c81f5ddb571d97 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs @@ -433,6 +433,122 @@ internal Arm64() { } /// public static Vector BitwiseSelectRightInverted(Vector select, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + /// Interleaving Xor + + /// + /// svint8_t sveorbt[_s8](svint8_t odd, svint8_t op1, svint8_t op2) + /// EORBT Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t sveorbt[_s16](svint16_t odd, svint16_t op1, svint16_t op2) + /// EORBT Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t sveorbt[_s32](svint32_t odd, svint32_t op1, svint32_t op2) + /// EORBT Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t sveorbt[_s64](svint64_t odd, svint64_t op1, svint64_t op2) + /// EORBT Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint8_t sveorbt[_s8](svint8_t odd, svint8_t op1, svint8_t op2) + /// EORBT Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t sveorbt[_s16](svint16_t odd, svint16_t op1, svint16_t op2) + /// EORBT Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t sveorbt[_s32](svint32_t odd, svint32_t op1, svint32_t op2) + /// EORBT Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t sveorbt[_s64](svint64_t odd, svint64_t op1, svint64_t op2) + /// EORBT Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint8_t sveortb[_s8](svint8_t even, svint8_t op1, svint8_t op2) + /// EORTB Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t sveortb[_s16](svint16_t even, svint16_t op1, svint16_t op2) + /// EORTB Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t sveortb[_s32](svint32_t even, svint32_t op1, svint32_t op2) + /// EORTB Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t sveortb[_s64](svint64_t even, svint64_t op1, svint64_t op2) + /// EORTB Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint8_t sveortb[_s8](svint8_t even, svint8_t op1, svint8_t op2) + /// EORTB Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint16_t sveortb[_s16](svint16_t even, svint16_t op1, svint16_t op2) + /// EORTB Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint32_t sveortb[_s32](svint32_t even, svint32_t op1, svint32_t op2) + /// EORTB Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + /// + /// svint64_t sveortb[_s64](svint64_t even, svint64_t op1, svint64_t op2) + /// EORTB Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + + + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } + // Rounding shift left diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.cs index 3e3e8defada286..bf387716677308 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.cs @@ -433,6 +433,104 @@ internal Arm64() { } /// public static unsafe Vector BitwiseSelectRightInverted(Vector select, Vector left, Vector right) => BitwiseSelectRightInverted(select, left, right); + /// Interleaving Xor + + /// + /// svint8_t sveorbt[_s8](svint8_t odd, svint8_t op1, svint8_t op2) + /// EORBT Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint16_t sveorbt[_s16](svint16_t odd, svint16_t op1, svint16_t op2) + /// EORBT Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint32_t sveorbt[_s32](svint32_t odd, svint32_t op1, svint32_t op2) + /// EORBT Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint64_t sveorbt[_s64](svint64_t odd, svint64_t op1, svint64_t op2) + /// EORBT Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint8_t sveorbt[_s8](svint8_t odd, svint8_t op1, svint8_t op2) + /// EORBT Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint16_t sveorbt[_s16](svint16_t odd, svint16_t op1, svint16_t op2) + /// EORBT Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint32_t sveorbt[_s32](svint32_t odd, svint32_t op1, svint32_t op2) + /// EORBT Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint64_t sveorbt[_s64](svint64_t odd, svint64_t op1, svint64_t op2) + /// EORBT Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) => InterleavingXorEvenOdd(odd, left, right); + + /// + /// svint8_t sveortb[_s8](svint8_t even, svint8_t op1, svint8_t op2) + /// EORTB Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint16_t sveortb[_s16](svint16_t even, svint16_t op1, svint16_t op2) + /// EORTB Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint32_t sveortb[_s32](svint32_t even, svint32_t op1, svint32_t op2) + /// EORTB Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint64_t sveortb[_s64](svint64_t even, svint64_t op1, svint64_t op2) + /// EORTB Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint8_t sveortb[_s8](svint8_t even, svint8_t op1, svint8_t op2) + /// EORTB Zd.B, Zn.B, Zm.B + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint16_t sveortb[_s16](svint16_t even, svint16_t op1, svint16_t op2) + /// EORTB Zd.H, Zn.H, Zm.H + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint32_t sveortb[_s32](svint32_t even, svint32_t op1, svint32_t op2) + /// EORTB Zd.S, Zn.S, Zm.S + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + + /// + /// svint64_t sveortb[_s64](svint64_t even, svint64_t op1, svint64_t op2) + /// EORTB Zd.D, Zn.D, Zm.D + /// + public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) => InterleavingXorOddEven(even, left, right); + // Rounding shift left diff --git a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs index 00c08ac75de140..997220f0dac0a6 100644 --- a/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs +++ b/src/libraries/System.Runtime.Intrinsics/ref/System.Runtime.Intrinsics.cs @@ -6148,6 +6148,22 @@ internal Arm64() { } public static System.Numerics.Vector BitwiseSelectRightInverted(System.Numerics.Vector select, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector BitwiseSelectRightInverted(System.Numerics.Vector select, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector BitwiseSelectRightInverted(System.Numerics.Vector select, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorEvenOdd(System.Numerics.Vector odd, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } + public static System.Numerics.Vector InterleavingXorOddEven(System.Numerics.Vector even, System.Numerics.Vector left, System.Numerics.Vector right) { throw null; } public static System.Numerics.Vector ShiftArithmeticRounded(System.Numerics.Vector value, System.Numerics.Vector count) { throw null; } public static System.Numerics.Vector ShiftArithmeticRounded(System.Numerics.Vector value, System.Numerics.Vector count) { throw null; } public static System.Numerics.Vector ShiftArithmeticRounded(System.Numerics.Vector value, System.Numerics.Vector count) { throw null; } diff --git a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs index 87f868fc04aa0e..07dda5038c4894 100644 --- a/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs +++ b/src/tests/Common/GenerateHWIntrinsicTests/GenerateHWIntrinsicTests_Arm.cs @@ -4851,6 +4851,23 @@ ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_BitwiseSelectRightInverted_uint", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "BitwiseSelectRightInverted", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt32()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.BitwiseSelectRightInverted(firstOp[i], secondOp[i], thirdOp[i])", ["GetIterResult"] = "Helpers.BitwiseSelectRightInverted(firstOp[i], secondOp[i], thirdOp[i])"}), ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_BitwiseSelectRightInverted_ulong", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "BitwiseSelectRightInverted", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt64()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.BitwiseSelectRightInverted(firstOp[i], secondOp[i], thirdOp[i])", ["GetIterResult"] = "Helpers.BitwiseSelectRightInverted(firstOp[i], secondOp[i], thirdOp[i])"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_byte", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["NextValueOp3"] = "TestLibrary.Generator.GetByte()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_short", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp3"] = "TestLibrary.Generator.GetInt16()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_int", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp3"] = "TestLibrary.Generator.GetInt32()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_long", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp3"] = "TestLibrary.Generator.GetInt64()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_sbyte", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp3"] = "TestLibrary.Generator.GetSByte()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_ushort", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt16()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_uint", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt32()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorEvenOdd_ulong", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorEvenOdd", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt64()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorEvenOdd(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorEvenOdd(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_byte", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Byte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Byte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Byte", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Byte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetByte()", ["NextValueOp3"] = "TestLibrary.Generator.GetByte()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_short", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp3"] = "TestLibrary.Generator.GetInt16()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_int", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp3"] = "TestLibrary.Generator.GetInt32()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_long", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int64", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "Int64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt64()", ["NextValueOp3"] = "TestLibrary.Generator.GetInt64()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_sbyte", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp3"] = "TestLibrary.Generator.GetSByte()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_ushort", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt16", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt16()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt16()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_uint", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt32", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt32()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt32()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecTernOpTest.template", new Dictionary { ["TestName"] = "Sve2_InterleavingXorOddEven_ulong", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "InterleavingXorOddEven", ["RetVectorType"] = "Vector", ["RetBaseType"] = "UInt64", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "UInt64", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "UInt64", ["Op3VectorType"] = "Vector", ["Op3BaseType"] = "UInt64", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp2"] = "TestLibrary.Generator.GetUInt64()", ["NextValueOp3"] = "TestLibrary.Generator.GetUInt64()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != Helpers.InterleavingXorOddEven(firstOp, secondOp, thirdOp)[i]", ["GetIterResult"] = "Helpers.InterleavingXorOddEven(first, second, third)[i]"}), + ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve2_ShiftArithmeticRounded_sbyte", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "ShiftArithmeticRounded", ["RetVectorType"] = "Vector", ["RetBaseType"] = "SByte", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "SByte", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "SByte", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetSByte()", ["NextValueOp2"] = "TestLibrary.Generator.GetSByte()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != (sbyte)Helpers.SveShiftArithmeticRounded(left[i], right[i])", ["GetIterResult"] = "(sbyte)Helpers.SveShiftArithmeticRounded(leftOp[i], rightOp[i])"}), ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve2_ShiftArithmeticRounded_short", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "ShiftArithmeticRounded", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int16", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int16", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int16", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt16()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt16()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != (short)Helpers.SveShiftArithmeticRounded(left[i], right[i])", ["GetIterResult"] = "(short)Helpers.SveShiftArithmeticRounded(leftOp[i], rightOp[i])"}), ("SveVecBinOpTest.template", new Dictionary { ["TestName"] = "Sve2_ShiftArithmeticRounded_int", ["Isa"] = "Sve2", ["LoadIsa"] = "Sve2", ["Method"] = "ShiftArithmeticRounded", ["RetVectorType"] = "Vector", ["RetBaseType"] = "Int32", ["Op1VectorType"] = "Vector", ["Op1BaseType"] = "Int32", ["Op2VectorType"] = "Vector", ["Op2BaseType"] = "Int32", ["LargestVectorSize"] = "64", ["NextValueOp1"] = "TestLibrary.Generator.GetInt32()", ["NextValueOp2"] = "TestLibrary.Generator.GetInt32()", ["ConvertFunc"] = "", ["ValidateIterResult"] = "result[i] != (int) Helpers.SveShiftArithmeticRounded(left[i], right[i])", ["GetIterResult"] = "(int) Helpers.SveShiftArithmeticRounded(leftOp[i], rightOp[i])"}), diff --git a/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs b/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs index 74d955d08456f3..abc6336052ada1 100644 --- a/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs +++ b/src/tests/JIT/HardwareIntrinsics/Arm/Shared/Helpers.cs @@ -10494,6 +10494,24 @@ public static T BitwiseSelectRightInverted(T select, T left, T right) where T return (left & select) | (~right & ~select); } + public static T[] InterleavingXorEvenOdd(T[] odd, T[] left, T[] right) where T : IBinaryInteger + { + for (int i = 0; i < odd.Length; i += 2) + { + odd[i] = left[i] ^ right[i + 1]; + } + return odd; + } + + public static T[] InterleavingXorOddEven(T[] even, T[] left, T[] right) where T : IBinaryInteger + { + for (int i = 0; i < even.Length; i += 2) + { + even[i+1] = left[i+1] ^ right[i]; + } + return even; + } + public static T Xor(params T[] ops) where T : IBitwiseOperators { T result = ops[0]; From 5ab918b9f0d8a27dd4487d2491547827b2b66bb5 Mon Sep 17 00:00:00 2001 From: Jonathan Davies Date: Thu, 12 Jun 2025 12:29:33 +0000 Subject: [PATCH 2/3] Remove duplicate functions --- src/coreclr/jit/hwintrinsiclistarm64sve.h | 4 ++-- .../Arm/Sve2.PlatformNotSupported.cs | 18 ------------------ 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h index 3da02ce85787bf..d1fe2a6bac6741 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64sve.h +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -322,8 +322,8 @@ HARDWARE_INTRINSIC(Sve2, BitwiseClearXor, HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, {INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, BitwiseSelectRightInverted, -1, 3, {INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) -HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics) -HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics) +HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable) +HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRounded, -1, -1, {INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRoundedSaturate, -1, -1, {INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticSaturate, -1, -1, {INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) diff --git a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs index c81f5ddb571d97..a2dc852245c801 100644 --- a/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs +++ b/src/libraries/System.Private.CoreLib/src/System/Runtime/Intrinsics/Arm/Sve2.PlatformNotSupported.cs @@ -532,24 +532,6 @@ internal Arm64() { } public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorEvenOdd(Vector odd, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - public static unsafe Vector InterleavingXorOddEven(Vector even, Vector left, Vector right) { throw new PlatformNotSupportedException(); } - - // Rounding shift left /// From 3d445d09459da570a57dcfb351718167059a9bd9 Mon Sep 17 00:00:00 2001 From: Jonathan Davies Date: Fri, 13 Jun 2025 09:53:46 +0000 Subject: [PATCH 3/3] Add RWM flag --- src/coreclr/jit/hwintrinsiclistarm64sve.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/hwintrinsiclistarm64sve.h b/src/coreclr/jit/hwintrinsiclistarm64sve.h index d1fe2a6bac6741..3da02ce85787bf 100644 --- a/src/coreclr/jit/hwintrinsiclistarm64sve.h +++ b/src/coreclr/jit/hwintrinsiclistarm64sve.h @@ -322,8 +322,8 @@ HARDWARE_INTRINSIC(Sve2, BitwiseClearXor, HARDWARE_INTRINSIC(Sve2, BitwiseSelect, -1, 3, {INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_sve_bsl, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, BitwiseSelectLeftInverted, -1, 3, {INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_sve_bsl1n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, BitwiseSelectRightInverted, -1, 3, {INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_sve_bsl2n, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_SpecialCodeGen|HW_Flag_HasRMWSemantics) -HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable) -HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable) +HARDWARE_INTRINSIC(Sve2, InterleavingXorEvenOdd, -1, 3, {INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_sve_eorbt, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics) +HARDWARE_INTRINSIC(Sve2, InterleavingXorOddEven, -1, 3, {INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_sve_eortb, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_HasRMWSemantics) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRounded, -1, -1, {INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_sve_srshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticRoundedSaturate, -1, -1, {INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_sve_sqrshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation) HARDWARE_INTRINSIC(Sve2, ShiftArithmeticSaturate, -1, -1, {INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_sve_sqshl, INS_invalid, INS_invalid, INS_invalid}, HW_Category_SIMD, HW_Flag_Scalable|HW_Flag_EmbeddedMaskedOperation|HW_Flag_HasRMWSemantics|HW_Flag_LowMaskedOperation)