diff --git a/src/coreclr/jit/instr.cpp b/src/coreclr/jit/instr.cpp index 9d505f973bdfc7..a0dbcaab36f34a 100644 --- a/src/coreclr/jit/instr.cpp +++ b/src/coreclr/jit/instr.cpp @@ -901,7 +901,7 @@ CodeGen::OperandDesc CodeGen::genOperandDesc(GenTree* op) // handle other cases recursively. GenTree* hwintrinsicChild = hwintrinsic->Op(1); assert(hwintrinsicChild->isContained()); - if (hwintrinsicChild->OperIs(GT_CNS_INT, GT_CNS_LNG)) + if (hwintrinsicChild->IsIntegralConst()) { // a special case is when the operand of CreateScalarUnsafe is an integer type, // CreateScalarUnsafe node will be folded, so we directly match a pattern of diff --git a/src/coreclr/jit/lowerxarch.cpp b/src/coreclr/jit/lowerxarch.cpp index 0055b8693a32ad..ec09d073b1aab8 100644 --- a/src/coreclr/jit/lowerxarch.cpp +++ b/src/coreclr/jit/lowerxarch.cpp @@ -9127,7 +9127,7 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre if (IsInvariantInRange(op1, parentNode, hwintrinsic)) { - if (op1->isContained()) + if (op1->isContained() && !op1->OperIsLong()) { // We have CreateScalarUnsafe where the underlying scalar is contained // As such, we can contain the CreateScalarUnsafe and consume the value @@ -9207,10 +9207,12 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre if (broadcastOperand->OperIsHWIntrinsic()) { GenTreeHWIntrinsic* hwintrinsicOperand = broadcastOperand->AsHWIntrinsic(); + NamedIntrinsic operandIntrinsicId = hwintrinsicOperand->GetHWIntrinsicId(); - if (HWIntrinsicInfo::IsVectorCreateScalarUnsafe(hwintrinsicOperand->GetHWIntrinsicId())) + if (HWIntrinsicInfo::IsVectorCreateScalar(operandIntrinsicId) || + HWIntrinsicInfo::IsVectorCreateScalarUnsafe(operandIntrinsicId)) { - // CreateScalarUnsafe can contain non-memory operands such as enregistered + // CreateScalar/Unsafe can contain non-memory operands such as enregistered // locals, so we want to check if its operand is containable instead. This // will result in such enregistered locals returning `false`. broadcastOperand = hwintrinsicOperand->Op(1); diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_113832/Runtime_113832.cs b/src/tests/JIT/Regression/JitBlue/Runtime_113832/Runtime_113832.cs index 092f9cdcf1075f..f3b580c14c8a2a 100644 --- a/src/tests/JIT/Regression/JitBlue/Runtime_113832/Runtime_113832.cs +++ b/src/tests/JIT/Regression/JitBlue/Runtime_113832/Runtime_113832.cs @@ -5,8 +5,15 @@ // Run on X86 Windows // Seed: 916448399438567841-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86bmi1,x86bmi2,x86fma,x86lzcnt,x86pclmulqdq,x86popcnt,x86sse,x86sse2,x86sse3,x86sse41,x86sse42,x86ssse3,x86x86base // Reduced from 63.4 KiB to 0.7 KiB in 00:02:21 -// Hits JIT assert in Release: +// Problem() Hits JIT assert in Release: // Assertion failed '(consume == 0) || (ComputeAvailableSrcCount(tree) == consume)' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Linear scan register alloc' (IL size 68; hash 0xade6b36b; FullOpts) + +// Generated by Fuzzlyn v2.5 on 2025-03-27 16:58:00 +// Run on X86 Windows +// Seed: 10696738320409793384-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86bmi1,x86bmi2,x86fma,x86lzcnt,x86pclmulqdq,x86popcnt,x86sse,x86sse2,x86sse3,x86sse41,x86sse42,x86ssse3,x86x86base +// Reduced from 151.7 KiB to 0.8 KiB in 00:02:43 +// Problem2() Hits JIT assert in Release: +// Assertion failed 'hwintrinsicChild->isContained()' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Generate code' (IL size 94; hash 0xade6b36b; FullOpts) using System; using System.Runtime.Intrinsics; using System.Runtime.Intrinsics.X86; @@ -33,4 +40,27 @@ public static void Problem() Console.WriteLine(vr17); } } + + public static ulong s_26; + + [Fact] + public static void Problem2() + { + if (Avx512F.VL.IsSupported) + { + Vector256 vr14 = default; + var vr15 = s_26++; + var vr16 = Vector128.CreateScalar(vr15); + var vr17 = Avx2.BroadcastScalarToVector128(vr16); + var vr18 = Vector128.Create(0); + var vr19 = Vector128.Create(0); + var vr20 = Sse2.ShiftRightLogical128BitLane(vr19, 0); + var vr21 = Avx512F.VL.PermuteVar2x64x2(vr17, vr18, vr20); + var vr22 = Vector128.Create(0); + if (Sse41.TestZ(vr21, vr22)) + { + Console.WriteLine(vr14); + } + } + } }