From 7217ce7f0906e1fac61055ca09c91e7b03f4470f Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Thu, 1 Aug 2024 16:01:18 +0100 Subject: [PATCH 1/8] ARM64-SVE: Avoid containing non-embedded conditional select --- src/coreclr/jit/lowerarmarch.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index a227d8ac14148a..0aa49cfeddb91a 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -3919,11 +3919,11 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node) } // Handle op3 - if (op3->IsVectorZero() && op1->IsMaskAllBitsSet()) + if (op3->IsVectorZero() && op1->IsMaskAllBitsSet() && op2->IsEmbMaskOp()) { // When we are merging with zero, we can specialize // and avoid instantiating the vector constant. - // Do this only if op1 was AllTrueMask + // Do this only if op1 was AllTrueMask and op2 is embedded. MakeSrcContained(node, op3); } From c687825d7b1d8621552f0a83db182002c63bbf5f Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Mon, 5 Aug 2024 11:47:51 +0100 Subject: [PATCH 2/8] Add test --- .../JitBlue/Runtime_105719/Runtime_105719.cs | 31 +++++++++++++++++++ .../Runtime_105719/Runtime_105719.csproj | 12 +++++++ 2 files changed, 43 insertions(+) create mode 100644 src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.cs create mode 100644 src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.cs b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.cs new file mode 100644 index 00000000000000..c8eff043c9bdad --- /dev/null +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.cs @@ -0,0 +1,31 @@ +// Licensed to the .NET Foundation under one or more agreements. +// The .NET Foundation licenses this file to you under the MIT license. + +using Xunit; +using System; +using System.Runtime.CompilerServices; +using System.Numerics; +using System.Runtime.Intrinsics; +using System.Runtime.Intrinsics.Arm; + +public class Runtime_105723 +{ + [Fact] + public static void TestEntryPoint() + { + if (Sve.IsSupported) + { + var vr3 = Sve.CreateTrueMaskInt32(); + var vr4 = Vector.Create(1); + var vr5 = Vector128.CreateScalar(0).AsVector(); + Vector vr6 = Sve.ConditionalSelect(vr3, vr4, vr5); + Consume(vr6); + } + } + + [MethodImpl(MethodImplOptions.NoInlining)] + private static void Consume(Vector v) + { + ; + } +} diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj new file mode 100644 index 00000000000000..c4ca5d2088961f --- /dev/null +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj @@ -0,0 +1,12 @@ + + + + true + True + + + + + + + From 29cadd5e47b6669def24886cac2ab711f92b82bc Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Mon, 5 Aug 2024 12:06:35 +0100 Subject: [PATCH 3/8] Minimal test csproj file --- .../Regression/JitBlue/Runtime_105719/Runtime_105719.csproj | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj index c4ca5d2088961f..de6d5e08882e86 100644 --- a/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj @@ -1,12 +1,8 @@ - - true True - - From 37ac806653f365192ceceb8f467e5e4eb8ce2842 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Mon, 5 Aug 2024 17:27:46 +0100 Subject: [PATCH 4/8] Add NoWarn --- .../JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj | 1 + 1 file changed, 1 insertion(+) diff --git a/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj index de6d5e08882e86..bb40d49ed68241 100644 --- a/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj +++ b/src/tests/JIT/Regression/JitBlue/Runtime_105719/Runtime_105719.csproj @@ -1,6 +1,7 @@ True + $(NoWarn);SYSLIB5003 From b86f18b86224938bff7038f58978620c70945270 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 6 Aug 2024 14:25:24 +0100 Subject: [PATCH 5/8] Remove conditionalselect --- src/coreclr/jit/lowerarmarch.cpp | 49 +++++++++++++++++++++++++++++--- 1 file changed, 45 insertions(+), 4 deletions(-) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index 0aa49cfeddb91a..7b414ce07965fd 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -3919,11 +3919,11 @@ void Lowering::ContainCheckHWIntrinsic(GenTreeHWIntrinsic* node) } // Handle op3 - if (op3->IsVectorZero() && op1->IsMaskAllBitsSet() && op2->IsEmbMaskOp()) + if (op3->IsVectorZero() && op1->IsMaskAllBitsSet()) { // When we are merging with zero, we can specialize // and avoid instantiating the vector constant. - // Do this only if op1 was AllTrueMask and op2 is embedded. + // Do this only if op1 was AllTrueMask MakeSrcContained(node, op3); } @@ -4035,7 +4035,7 @@ GenTree* Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* cndSelNode) GenTree* nestedOp2 = nestedCndSel->Op(2); GenTree* nestedOp3 = nestedCndSel->Op(3); - JITDUMP("lowering ConditionalSelect HWIntrinisic (before):\n"); + JITDUMP("lowering nested ConditionalSelect HWIntrinisic (before):\n"); DISPTREERANGE(BlockRange(), cndSelNode); JITDUMP("\n"); @@ -4057,13 +4057,54 @@ GenTree* Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* cndSelNode) BlockRange().Remove(nestedOp1); BlockRange().Remove(nestedCndSel); - JITDUMP("lowering ConditionalSelect HWIntrinisic (after):\n"); + JITDUMP("lowering nested ConditionalSelect HWIntrinisic (after):\n"); DISPTREERANGE(BlockRange(), cndSelNode); JITDUMP("\n"); return cndSelNode; } } + else if (op1->IsMaskAllBitsSet()) + { + // Any case where op2 is not an embedded HWIntrinsic + if (!op2->OperIsHWIntrinsic() || !HWIntrinsicInfo::IsEmbeddedMaskedOperation(op2->AsHWIntrinsic()->GetHWIntrinsicId())) + { + JITDUMP("lowering ConditionalSelect HWIntrinisic (before):\n"); + DISPTREERANGE(BlockRange(), cndSelNode); + JITDUMP("\n"); + + // Transform + // CndSel(AllTrue, op2, op3) to + // op2 + + LIR::Use use; + if (BlockRange().TryGetUse(cndSelNode, &use)) + { + use.ReplaceWith(op2); + } + else + { + op2->SetUnusedValue(); + } + + if (op3->IsMaskZero()) + { + BlockRange().Remove(op3); + } + else + { + op3->SetUnusedValue(); + } + op1->SetUnusedValue(); + BlockRange().Remove(cndSelNode); + + JITDUMP("lowering ConditionalSelect HWIntrinisic (after):\n"); + DISPTREERANGE(BlockRange(), op2); + JITDUMP("\n"); + + return op2; + } + } ContainCheckHWIntrinsic(cndSelNode); return cndSelNode->gtNext; From 2d4d006ba5e72833d8950ba7798208244863f16f Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Tue, 6 Aug 2024 16:09:14 +0100 Subject: [PATCH 6/8] Fix formatting --- src/coreclr/jit/lowerarmarch.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/coreclr/jit/lowerarmarch.cpp b/src/coreclr/jit/lowerarmarch.cpp index 7b414ce07965fd..5612b44896ec8d 100644 --- a/src/coreclr/jit/lowerarmarch.cpp +++ b/src/coreclr/jit/lowerarmarch.cpp @@ -4067,7 +4067,8 @@ GenTree* Lowering::LowerHWIntrinsicCndSel(GenTreeHWIntrinsic* cndSelNode) else if (op1->IsMaskAllBitsSet()) { // Any case where op2 is not an embedded HWIntrinsic - if (!op2->OperIsHWIntrinsic() || !HWIntrinsicInfo::IsEmbeddedMaskedOperation(op2->AsHWIntrinsic()->GetHWIntrinsicId())) + if (!op2->OperIsHWIntrinsic() || + !HWIntrinsicInfo::IsEmbeddedMaskedOperation(op2->AsHWIntrinsic()->GetHWIntrinsicId())) { JITDUMP("lowering ConditionalSelect HWIntrinisic (before):\n"); DISPTREERANGE(BlockRange(), cndSelNode); From f76d1d2888bceda49e840864c3062731dc99207a Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 7 Aug 2024 11:34:02 +0100 Subject: [PATCH 7/8] Add lowerarmarch.cpp to SVE CI testing --- eng/pipelines/coreclr/jitstress-isas-sve.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/eng/pipelines/coreclr/jitstress-isas-sve.yml b/eng/pipelines/coreclr/jitstress-isas-sve.yml index ec27ba55c3ed0c..0779521faa3f5b 100644 --- a/eng/pipelines/coreclr/jitstress-isas-sve.yml +++ b/eng/pipelines/coreclr/jitstress-isas-sve.yml @@ -15,6 +15,7 @@ pr: - src/coreclr/jit/emitarm64sve.cpp - src/coreclr/jit/emitfmtsarm64sve.h - src/coreclr/jit/lsraarm64.cpp + - src/coreclr/jit/lowerarmarch.cpp schedules: - cron: "30 19 * * 6" From cd7cd94619991a73ca5559660783fa6507460cb3 Mon Sep 17 00:00:00 2001 From: Alan Hayward Date: Wed, 7 Aug 2024 13:55:37 +0100 Subject: [PATCH 8/8] More SVE CI testing entries --- eng/pipelines/coreclr/jitstress-isas-sve.yml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/eng/pipelines/coreclr/jitstress-isas-sve.yml b/eng/pipelines/coreclr/jitstress-isas-sve.yml index 0779521faa3f5b..c5aca49e62322f 100644 --- a/eng/pipelines/coreclr/jitstress-isas-sve.yml +++ b/eng/pipelines/coreclr/jitstress-isas-sve.yml @@ -8,14 +8,16 @@ pr: - main paths: include: + - src/coreclr/jit/codegenarmarch.cpp + - src/coreclr/jit/emitarm64sve.cpp + - src/coreclr/jit/emitfmtsarm64sve.h + - src/coreclr/jit/hwintrinsicarm64.cpp - src/coreclr/jit/hwintrinsiccodegenarm64.cpp - src/coreclr/jit/hwintrinsiclistarm64sve.h - - src/coreclr/jit/hwintrinsicarm64.cpp - src/coreclr/jit/instrsarm64sve.h - - src/coreclr/jit/emitarm64sve.cpp - - src/coreclr/jit/emitfmtsarm64sve.h - - src/coreclr/jit/lsraarm64.cpp - src/coreclr/jit/lowerarmarch.cpp + - src/coreclr/jit/lsraarmarch.cpp + - src/coreclr/jit/lsraarm64.cpp schedules: - cron: "30 19 * * 6"