Loongarch/riscV: ThreadLocal optimization during JIT should detect static/dynamic resolver

[kunalspathak]

The JIT code today assume that static resolver will give us a small offset that we embed in JIT. However, with dynamic resolver, the offset returned can that be of current thread, and embedding it in JIT code might be problematic. We are addressing the problem for arm64 in #104408, but might have to do similar thing (after validation) for loongarch/riscv

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[jkotas]

cc @shushanhf @dotnet/samsung

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[JulieLeeMSFT]

Ping @shushanhf, @dotnet/samsung if you can look into this. RC1 snap is 8/14.

[shushanhf]

Ping @shushanhf, @dotnet/samsung if you can look into this. RC1 snap is 8/14.

@kunalspathak @JulieLeeMSFT
The #104408 is still in progress. Do you merge the #104408 within the RC1? And should I reference the #104408 for LA64？

[davidwrighton]

@shushanhf @dotnet/samsung This is now fixed as of the merge of PR #106052. You should be able to write a followup PR for each of your architectures that fixes this problem for your scenarios.

[shushanhf]

@shushanhf @dotnet/samsung This is now fixed as of the merge of PR #106052. You should be able to write a followup PR for each of your architectures that fixes this problem for your scenarios.

OK,Thanks

[JulieLeeMSFT]

Fixed by #106250 .

[jkotas]

#106250 fixed this for Loongarch. We still need a fix for RiscV.

[clamp03]

@tomeksowi Could you fix this for RISC-V? Thank you.

[clamp03]

@tomeksowi If you can't, please assign to a member in SRPOL.

[tomeksowi]

@tomeksowi Could you fix this for RISC-V? Thank you.

OK, I'll take it.

[tomeksowi]

Update: I got an implementation for RISC-V but now corerun is crashing:

Failed to load: '/runtime/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/libcoreclr.so'. Error: /runtime/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/libcoreclr.so: unexpected reloc type 0x0c

where reloc type 0x0c is TLSDESC on RISC-V ELF.

Not sure if that has something to do with tlsdesc being fairly recent addition to RISC-V toolchain. @dotnet/samsung If anyone has an idea, I'd be grateful.