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Loongarch/riscV: ThreadLocal optimization during JIT should detect static/dynamic resolver #104518

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kunalspathak opened this issue Jul 7, 2024 · 13 comments
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arch-riscv Related to the RISC-V architecture area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
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@kunalspathak
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The JIT code today assume that static resolver will give us a small offset that we embed in JIT. However, with dynamic resolver, the offset returned can that be of current thread, and embedding it in JIT code might be problematic. We are addressing the problem for arm64 in #104408, but might have to do similar thing (after validation) for loongarch/riscv

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jul 7, 2024
@dotnet-policy-service dotnet-policy-service bot added the untriaged New issue has not been triaged by the area owner label Jul 7, 2024
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@jkotas
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jkotas commented Jul 7, 2024

cc @shushanhf @dotnet/samsung

@JulieLeeMSFT JulieLeeMSFT added this to the 9.0.0 milestone Jul 8, 2024
@JulieLeeMSFT JulieLeeMSFT removed the untriaged New issue has not been triaged by the area owner label Jul 8, 2024
@JulieLeeMSFT JulieLeeMSFT added the needs-author-action An issue or pull request that requires more info or actions from the author. label Aug 1, 2024
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This issue has been marked needs-author-action and may be missing some important information.

@JulieLeeMSFT
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Ping @shushanhf, @dotnet/samsung if you can look into this. RC1 snap is 8/14.

@shushanhf
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Ping @shushanhf, @dotnet/samsung if you can look into this. RC1 snap is 8/14.

@kunalspathak @JulieLeeMSFT
The #104408 is still in progress. Do you merge the #104408 within the RC1? And should I reference the #104408 for LA64?

@davidwrighton
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@shushanhf @dotnet/samsung This is now fixed as of the merge of PR #106052. You should be able to write a followup PR for each of your architectures that fixes this problem for your scenarios.

@shushanhf
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@shushanhf @dotnet/samsung This is now fixed as of the merge of PR #106052. You should be able to write a followup PR for each of your architectures that fixes this problem for your scenarios.

OK,Thanks

@JulieLeeMSFT
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Fixed by #106250 .

@jkotas
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jkotas commented Aug 12, 2024

#106250 fixed this for Loongarch. We still need a fix for RiscV.

@jkotas jkotas reopened this Aug 12, 2024
@jkotas jkotas modified the milestones: 9.0.0, 10.0.0 Aug 12, 2024
@jkotas jkotas removed needs-author-action An issue or pull request that requires more info or actions from the author. arch-loongarch64 labels Aug 12, 2024
@clamp03
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clamp03 commented Aug 13, 2024

@tomeksowi Could you fix this for RISC-V? Thank you.

@clamp03
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clamp03 commented Aug 14, 2024

@tomeksowi If you can't, please assign to a member in SRPOL.

@tomeksowi
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@tomeksowi Could you fix this for RISC-V? Thank you.

OK, I'll take it.

@tomeksowi
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tomeksowi commented Aug 16, 2024

Update: I got an implementation for RISC-V but now corerun is crashing:

Failed to load: '/runtime/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/libcoreclr.so'. Error: /runtime/artifacts/tests/coreclr/linux.riscv64.Checked/Tests/Core_Root/libcoreclr.so: unexpected reloc type 0x0c

where reloc type 0x0c is TLSDESC on RISC-V ELF.

Not sure if that has something to do with tlsdesc being fairly recent addition to RISC-V toolchain. @dotnet/samsung If anyone has an idea, I'd be grateful.

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