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Arm64 SVE: Add mask to nonfaulting loads (#117606)
Fixes #108234 SveLoadNonFaultingMaskedUnOpTest.template is a mixture of SveLoadNonFaultingUnOpTest.template and SveLoadVectorMaskedTest.template
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13 files changed

+757
-736
lines changed

13 files changed

+757
-736
lines changed

‎src/coreclr/inc/jiteeversionguid.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,11 +37,11 @@
3737

3838
#include <minipal/guid.h>
3939

40-
constexpr GUID JITEEVersionIdentifier = { /* 5c7eb9f1-a9cb-4a35-aea6-ae93d1f54c56 */
41-
0x5c7eb9f1,
42-
0xa9cb,
43-
0x4a35,
44-
{0xae, 0xa6, 0xae, 0x93, 0xd1, 0xf5, 0x4c, 0x56}
40+
constexpr GUID JITEEVersionIdentifier = { /* 952f0344-7651-46af-8ef3-a34539af5c4a */
41+
0x952f0344,
42+
0x7651,
43+
0x46af,
44+
{0x8e, 0xf3, 0xa3, 0x45, 0x39, 0xaf, 0x5c, 0x4a}
4545
};
4646

4747
#endif // JIT_EE_VERSIONING_GUID_H

‎src/coreclr/jit/gentree.cpp‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28651,6 +28651,31 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
2865128651
case NI_Sve_Load2xVectorAndUnzip:
2865228652
case NI_Sve_Load3xVectorAndUnzip:
2865328653
case NI_Sve_Load4xVectorAndUnzip:
28654+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
28655+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
28656+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
28657+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
28658+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
28659+
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
28660+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
28661+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
28662+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
28663+
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
28664+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
28665+
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
28666+
case NI_Sve_LoadVectorNonFaulting:
28667+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
28668+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
28669+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
28670+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
28671+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
28672+
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
28673+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
28674+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
28675+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
28676+
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
28677+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
28678+
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
2865428679
addr = Op(2);
2865528680
break;
2865628681

‎src/coreclr/jit/hwintrinsiccodegenarm64.cpp‎

Lines changed: 6 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -670,38 +670,6 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
670670
// Perform the actual "predicated" operation so that `embMaskOp1Reg` is the first operand..
671671
switch (intrinEmbMask.id)
672672
{
673-
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt16:
674-
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt32:
675-
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToInt64:
676-
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt16:
677-
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt32:
678-
case NI_Sve_LoadVectorByteNonFaultingZeroExtendToUInt64:
679-
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt32:
680-
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToInt64:
681-
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt32:
682-
case NI_Sve_LoadVectorInt16NonFaultingSignExtendToUInt64:
683-
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToInt64:
684-
case NI_Sve_LoadVectorInt32NonFaultingSignExtendToUInt64:
685-
case NI_Sve_LoadVectorNonFaulting:
686-
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt16:
687-
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt32:
688-
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToInt64:
689-
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt16:
690-
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt32:
691-
case NI_Sve_LoadVectorSByteNonFaultingSignExtendToUInt64:
692-
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt32:
693-
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToInt64:
694-
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt32:
695-
case NI_Sve_LoadVectorUInt16NonFaultingZeroExtendToUInt64:
696-
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
697-
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
698-
{
699-
700-
GetEmitter()->emitIns_R_R_R(insEmbMask, emitSize, targetReg, maskReg, embMaskOp1Reg,
701-
opt);
702-
break;
703-
}
704-
705673
case NI_Sve_And_Predicates:
706674
case NI_Sve_BitwiseClear_Predicates:
707675
case NI_Sve_Or_Predicates:
@@ -2175,14 +2143,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
21752143
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToInt64:
21762144
case NI_Sve_LoadVectorUInt32NonFaultingZeroExtendToUInt64:
21772145
{
2178-
if (intrin.numOperands == 2)
2146+
if (intrin.numOperands == 3)
21792147
{
2180-
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR
2181-
// register.
2182-
assert(op2Reg != REG_NA);
2183-
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op2Reg, opt);
2148+
// We have extra argument which means there is a "use" of FFR here. Restore it back in FFR register.
2149+
assert(op3Reg != REG_NA);
2150+
GetEmitter()->emitIns_R(INS_sve_wrffr, emitSize, op3Reg, opt);
21842151
}
2185-
GetEmitter()->emitIns_R_R(ins, emitSize, targetReg, op1Reg);
2152+
2153+
GetEmitter()->emitIns_R_R_R_I(ins, emitSize, targetReg, op1Reg, op2Reg, 0, opt);
21862154
break;
21872155
}
21882156

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