55// Run on X86 Windows 
66// Seed: 916448399438567841-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86bmi1,x86bmi2,x86fma,x86lzcnt,x86pclmulqdq,x86popcnt,x86sse,x86sse2,x86sse3,x86sse41,x86sse42,x86ssse3,x86x86base 
77// Reduced from 63.4 KiB to 0.7 KiB in 00:02:21 
8- // Hits JIT assert in Release: 
8+ // Problem()  Hits JIT assert in Release: 
99// Assertion failed '(consume == 0) || (ComputeAvailableSrcCount(tree) == consume)' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Linear scan register alloc' (IL size 68; hash 0xade6b36b; FullOpts) 
10+ 
11+ // Generated by Fuzzlyn v2.5 on 2025-03-27 16:58:00 
12+ // Run on X86 Windows 
13+ // Seed: 10696738320409793384-vectort,vector128,vector256,x86aes,x86avx,x86avx2,x86avx512bw,x86avx512bwvl,x86avx512cd,x86avx512cdvl,x86avx512dq,x86avx512dqvl,x86avx512f,x86avx512fvl,x86bmi1,x86bmi2,x86fma,x86lzcnt,x86pclmulqdq,x86popcnt,x86sse,x86sse2,x86sse3,x86sse41,x86sse42,x86ssse3,x86x86base 
14+ // Reduced from 151.7 KiB to 0.8 KiB in 00:02:43 
15+ // Problem2() Hits JIT assert in Release: 
16+ // Assertion failed 'hwintrinsicChild->isContained()' in 'Program:Main(Fuzzlyn.ExecutionServer.IRuntime)' during 'Generate code' (IL size 94; hash 0xade6b36b; FullOpts) 
1017using  System ; 
1118using  System . Runtime . Intrinsics ; 
1219using  System . Runtime . Intrinsics . X86 ; 
@@ -33,4 +40,27 @@ public static void Problem()
3340            Console . WriteLine ( vr17 ) ; 
3441        } 
3542    } 
43+ 
44+     public  static ulong  s_26 ; 
45+ 
46+     [ Fact ] 
47+     public  static void  Problem2 ( ) 
48+     { 
49+         if  ( Avx512F . VL . IsSupported ) 
50+         { 
51+             Vector256 < short >  vr14  =  default ; 
52+             var  vr15  =  s_26 ++ ; 
53+             var  vr16  =  Vector128 . CreateScalar ( vr15 ) ; 
54+             var  vr17  =  Avx2 . BroadcastScalarToVector128 ( vr16 ) ; 
55+             var  vr18  =  Vector128 . Create < ulong > ( 0 ) ; 
56+             var  vr19  =  Vector128 . Create < ulong > ( 0 ) ; 
57+             var  vr20  =  Sse2 . ShiftRightLogical128BitLane ( vr19 ,  0 ) ; 
58+             var  vr21  =  Avx512F . VL . PermuteVar2x64x2 ( vr17 ,  vr18 ,  vr20 ) ; 
59+             var  vr22  =  Vector128 . Create < ulong > ( 0 ) ; 
60+             if  ( Sse41 . TestZ ( vr21 ,  vr22 ) ) 
61+             { 
62+                 Console . WriteLine ( vr14 ) ; 
63+             } 
64+         } 
65+     } 
3666} 
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