JIT: Only look for integer temp regs in prolog generation (#118956)

jakobbotsch · web-flow · commit bd94b146570c · 2025-08-22T09:40:58.000+02:00
Otherwise we may end up with mask registers in this mask, and passing
that to `genFindLowestBit` hits asserts. We are in any case only
interested in integer registers here, so limit it to that.
diff --git a/src/coreclr/jit/codegencommon.cpp b/src/coreclr/jit/codegencommon.cpp
@@ -5035,7 +5035,7 @@ void CodeGen::genFnProlog()
     const bool isOSRx64Root = false;
 #endif // TARGET_AMD64
 
-    regMaskTP tempMask = initRegs & ~excludeMask & ~regSet.rsMaskResvd;
+    regMaskTP tempMask = initRegs & RBM_ALLINT & ~excludeMask & ~regSet.rsMaskResvd;
 
     if (tempMask != RBM_NONE)
     {

Original file line number	Diff line number	Diff line change
`@@ -5035,7 +5035,7 @@ void CodeGen::genFnProlog()`
`5035`	`5035`	`const bool isOSRx64Root = false;`
`5036`	`5036`	`#endif // TARGET_AMD64`
`5037`	`5037`
`5038`		`- regMaskTP tempMask = initRegs & ~excludeMask & ~regSet.rsMaskResvd;`
	`5038`	`+ regMaskTP tempMask = initRegs & RBM_ALLINT & ~excludeMask & ~regSet.rsMaskResvd;`
`5039`	`5039`
`5040`	`5040`	`if (tempMask != RBM_NONE)`
`5041`	`5041`	`{`