Skip to content

Commit 963c341

Browse files
Skip unused regs
1 parent 5363283 commit 963c341

File tree

3 files changed

+24
-8
lines changed

3 files changed

+24
-8
lines changed

src/coreclr/jit/lsra.cpp

Lines changed: 18 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4286,14 +4286,15 @@ void LinearScan::resetAllRegistersState()
42864286
clearAllNextIntervalRef();
42874287
clearAllSpillCost();
42884288

4289-
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT; reg = REG_NEXT(reg))
4289+
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT;)
42904290
{
42914291
RegRecord* physRegRecord = getRegisterRecord(reg);
42924292
#ifdef DEBUG
42934293
Interval* assignedInterval = physRegRecord->assignedInterval;
42944294
assert(assignedInterval == nullptr || assignedInterval->isConstant);
42954295
#endif
42964296
physRegRecord->assignedInterval = nullptr;
4297+
reg = physRegRecord->nextRegNum;
42974298
}
42984299
}
42994300

@@ -4896,12 +4897,13 @@ void LinearScan::allocateRegistersMinimal()
48964897
clearAllNextIntervalRef();
48974898
clearAllSpillCost();
48984899

4899-
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT; reg = REG_NEXT(reg))
4900+
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT;)
49004901
{
49014902
RegRecord* physRegRecord = getRegisterRecord(reg);
49024903
physRegRecord->recentRefPosition = nullptr;
49034904
updateNextFixedRefDispatch(physRegRecord, physRegRecord->firstRefPosition, killHead);
49044905
assert(physRegRecord->assignedInterval == nullptr);
4906+
reg = physRegRecord->nextRegNum;
49054907
}
49064908

49074909
#ifdef DEBUG
@@ -5559,7 +5561,7 @@ void LinearScan::allocateRegisters()
55595561
#endif // FEATURE_PARTIAL_SIMD_CALLEE_SAVE
55605562

55615563
resetRegState();
5562-
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT; reg = REG_NEXT(reg))
5564+
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT;)
55635565
{
55645566
RegRecord* physRegRecord = getRegisterRecord(reg);
55655567
physRegRecord->recentRefPosition = nullptr;
@@ -5585,6 +5587,7 @@ void LinearScan::allocateRegisters()
55855587
clearNextIntervalRef(reg, physRegRecord->registerType);
55865588
clearSpillCost(reg, physRegRecord->registerType);
55875589
}
5590+
reg = physRegRecord->nextRegNum;
55885591
}
55895592

55905593
#ifdef DEBUG
@@ -7878,7 +7881,7 @@ void LinearScan::resolveRegisters()
78787881
// are encountered.
78797882
if (localVarsEnregistered)
78807883
{
7881-
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT; reg = REG_NEXT(reg))
7884+
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT;)
78827885
{
78837886
RegRecord* physRegRecord = getRegisterRecord(reg);
78847887
Interval* assignedInterval = physRegRecord->assignedInterval;
@@ -7889,6 +7892,7 @@ void LinearScan::resolveRegisters()
78897892
}
78907893
physRegRecord->assignedInterval = nullptr;
78917894
physRegRecord->recentRefPosition = nullptr;
7895+
reg = physRegRecord->nextRegNum;
78927896
}
78937897

78947898
// Clear "recentRefPosition" for lclVar intervals
@@ -11803,17 +11807,18 @@ bool LinearScan::IsResolutionNode(LIR::Range& containingRange, GenTree* node)
1180311807
//
1180411808
void LinearScan::verifyFreeRegisters(regMaskTP regsToFree)
1180511809
{
11806-
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT; reg = REG_NEXT(reg))
11810+
for (regNumber reg = REG_FIRST; reg < AVAILABLE_REG_COUNT;)
1180711811
{
11808-
regMaskTP regMask = genRegMask(reg);
11812+
regMaskTP regMask = genRegMask(reg);
11813+
RegRecord* physRegRecord = getRegisterRecord(reg);
1180911814
// If this isn't available or if it's still waiting to be freed (i.e. it was in
1181011815
// delayRegsToFree and so now it's in regsToFree), then skip it.
1181111816
if ((regMask & allAvailableRegs & ~regsToFree).IsEmpty())
1181211817
{
11818+
reg = physRegRecord->nextRegNum;
1181311819
continue;
1181411820
}
11815-
RegRecord* physRegRecord = getRegisterRecord(reg);
11816-
Interval* assignedInterval = physRegRecord->assignedInterval;
11821+
Interval* assignedInterval = physRegRecord->assignedInterval;
1181711822
if (assignedInterval != nullptr)
1181811823
{
1181911824
bool isAssignedReg = (assignedInterval->physReg == reg);
@@ -11824,6 +11829,7 @@ void LinearScan::verifyFreeRegisters(regMaskTP regsToFree)
1182411829
{
1182511830
if (recentRefPosition->refType == RefTypeExpUse)
1182611831
{
11832+
reg = physRegRecord->nextRegNum;
1182711833
// We don't update anything on these, as they're just placeholders to extend the
1182811834
// lifetime.
1182911835
continue;
@@ -11832,6 +11838,7 @@ void LinearScan::verifyFreeRegisters(regMaskTP regsToFree)
1183211838
// For copyReg or moveReg, we don't have anything further to assert.
1183311839
if (recentRefPosition->copyReg || recentRefPosition->moveReg)
1183411840
{
11841+
reg = physRegRecord->nextRegNum;
1183511842
continue;
1183611843
}
1183711844
assert(assignedInterval->isConstant == isRegConstant(reg, assignedInterval->registerType));
@@ -11899,6 +11906,9 @@ void LinearScan::verifyFreeRegisters(regMaskTP regsToFree)
1189911906
{
1190011907
reg = REG_NEXT(reg);
1190111908
}
11909+
reg = REG_NEXT(reg);
11910+
#else
11911+
reg = physRegRecord->nextRegNum;
1190211912
#endif
1190311913
}
1190411914
}

src/coreclr/jit/lsra.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -521,6 +521,7 @@ class RegRecord : public Referenceable
521521
}
522522
#endif // FEATURE_MASKED_HW_INTRINSICS
523523
regNum = reg;
524+
nextRegNum = REG_NEXT(regNum);
524525
isCalleeSave = ((RBM_CALLEE_SAVED & genRegMask(reg)) != 0);
525526
}
526527

@@ -544,6 +545,7 @@ class RegRecord : public Referenceable
544545
Interval* previousInterval;
545546

546547
regNumber regNum;
548+
regNumber nextRegNum; // the next active register.
547549
bool isCalleeSave;
548550
unsigned char regOrder;
549551
};

src/coreclr/jit/lsrabuild.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1936,6 +1936,10 @@ void LinearScan::buildPhysRegRecords()
19361936
RegRecord* curr = &physRegs[reg];
19371937
curr->init(reg);
19381938
}
1939+
#if defined(TARGET_AMD64)
1940+
RegRecord* lastInt = &physRegs[get_REG_INT_LAST()];
1941+
lastInt->nextRegNum = REG_FP_FIRST;
1942+
#endif // TARGET_AMD64
19391943
for (unsigned int i = 0; i < lsraRegOrderSize; i++)
19401944
{
19411945
regNumber reg = lsraRegOrder[i];

0 commit comments

Comments
 (0)