diff --git a/src/coreclr/jit/codegenarm64.cpp b/src/coreclr/jit/codegenarm64.cpp index 20b791348d0ce..6be622511ab72 100644 --- a/src/coreclr/jit/codegenarm64.cpp +++ b/src/coreclr/jit/codegenarm64.cpp @@ -10114,6 +10114,7 @@ void CodeGen::genArm64EmitterUnitTests() genDefineTempLabel(genCreateTempLabel()); + // IF_SVE_AA_3A theEmitter->emitIns_R_R_R(INS_sve_and, EA_SCALABLE, REG_V0, REG_P1, REG_V2, INS_OPTS_SCALABLE_B); // AND ., /M, ., . theEmitter->emitIns_R_R_R(INS_sve_bic, EA_SCALABLE, REG_V3, REG_P4, REG_V5, @@ -10123,6 +10124,7 @@ void CodeGen::genArm64EmitterUnitTests() theEmitter->emitIns_R_R_R(INS_sve_orr, EA_SCALABLE, REG_V29, REG_P7, REG_V31, INS_OPTS_SCALABLE_D); // ORR ., /M, ., . + // IF_SVE_AB_3A theEmitter->emitIns_R_R_R(INS_sve_add, EA_SCALABLE, REG_V5, REG_P6, REG_V7, INS_OPTS_SCALABLE_B); // ADD ., /M, ., . theEmitter->emitIns_R_R_R(INS_sve_sub, EA_SCALABLE, REG_V15, REG_P7, REG_V29, @@ -10130,6 +10132,7 @@ void CodeGen::genArm64EmitterUnitTests() theEmitter->emitIns_R_R_R(INS_sve_subr, EA_SCALABLE, REG_V2, REG_P0, REG_V13, INS_OPTS_SCALABLE_S); // SUBR ., /M, ., . + // IF_SVE_AC_3A theEmitter->emitIns_R_R_R(INS_sve_sdiv, EA_SCALABLE, REG_V3, REG_P2, REG_V9, INS_OPTS_SCALABLE_S); // SDIV ., /M, ., . theEmitter->emitIns_R_R_R(INS_sve_sdivr, EA_SCALABLE, REG_V31, REG_P3, REG_V29, @@ -10139,6 +10142,7 @@ void CodeGen::genArm64EmitterUnitTests() theEmitter->emitIns_R_R_R(INS_sve_udivr, EA_SCALABLE, REG_V13, REG_P7, REG_V15, INS_OPTS_SCALABLE_D); // UDIVR ., /M, ., . + // IF_SVE_AD_3A theEmitter->emitIns_R_R_R(INS_sve_smax, EA_SCALABLE, REG_V24, REG_P0, REG_V2, INS_OPTS_SCALABLE_B); // SMAX ., /M, ., . theEmitter->emitIns_R_R_R(INS_sve_smin, EA_SCALABLE, REG_V9, REG_P1, REG_V27, @@ -10152,184 +10156,186 @@ void CodeGen::genArm64EmitterUnitTests() theEmitter->emitIns_R_R_R(INS_sve_umin, EA_SCALABLE, REG_V12, REG_P7, REG_V0, INS_OPTS_SCALABLE_D); // UMIN ., /M, ., . + // IF_SVE_AE_3A theEmitter->emitIns_R_R_R(INS_sve_mul, EA_SCALABLE, REG_V5, REG_P1, REG_V3, - INS_OPTS_SCALABLE_D); // IF_SVE_AE_3A /* MUL ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* MUL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_smulh, EA_SCALABLE, REG_V17, REG_P5, REG_V5, - INS_OPTS_SCALABLE_S); // IF_SVE_AE_3A /* SMULH ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* SMULH ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_umulh, EA_SCALABLE, REG_V12, REG_P2, REG_V24, - INS_OPTS_SCALABLE_B); // IF_SVE_AE_3A /* UMULH ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* UMULH ., /M, ., . */ + // IF_SVE_AN_3A theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V5, REG_P0, REG_V21, - INS_OPTS_SCALABLE_S); // IF_SVE_AN_3A /* ASR ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* ASR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_asrr, EA_SCALABLE, REG_V1, REG_P7, REG_V20, - INS_OPTS_SCALABLE_B); // IF_SVE_AN_3A /* ASRR ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* ASRR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V0, REG_P2, REG_V0, - INS_OPTS_SCALABLE_H); // IF_SVE_AN_3A /* LSL ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* LSL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_lslr, EA_SCALABLE, REG_V27, REG_P6, REG_V31, - INS_OPTS_SCALABLE_D); // IF_SVE_AN_3A /* LSLR ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* LSLR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V5, REG_P5, REG_V6, - INS_OPTS_SCALABLE_B); // IF_SVE_AN_3A /* LSR ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* LSR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_lsrr, EA_SCALABLE, REG_V15, REG_P4, REG_V17, - INS_OPTS_SCALABLE_S); // IF_SVE_AN_3A /* LSRR ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* LSRR ., /M, ., . */ + // IF_SVE_AO_3A theEmitter->emitIns_R_R_R(INS_sve_asr, EA_SCALABLE, REG_V4, REG_P3, REG_V24, - INS_OPTS_SCALABLE_WIDE_B); // IF_SVE_AO_3A /* ASR ., /M, ., .D - // */ + INS_OPTS_SCALABLE_WIDE_B); /* ASR ., /M, ., .D */ theEmitter->emitIns_R_R_R(INS_sve_lsl, EA_SCALABLE, REG_V19, REG_P7, REG_V3, - INS_OPTS_SCALABLE_WIDE_H); // IF_SVE_AO_3A /* LSL ., /M, ., .D - // */ + INS_OPTS_SCALABLE_WIDE_H); /* LSL ., /M, ., .D */ theEmitter->emitIns_R_R_R(INS_sve_lsr, EA_SCALABLE, REG_V0, REG_P0, REG_V0, - INS_OPTS_SCALABLE_WIDE_S); // IF_SVE_AO_3A /* LSR ., /M, ., .D - // */ + INS_OPTS_SCALABLE_WIDE_S); /* LSR ., /M, ., .D */ + // IF_SVE_CM_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_SCALABLE, REG_V31, REG_P7, REG_V31, - INS_OPTS_SCALABLE_B); // IF_SVE_CM_3A /* CLASTA ., , ., . */ + INS_OPTS_SCALABLE_B); /* CLASTA ., , ., . */ theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_SCALABLE, REG_V30, REG_P6, REG_V30, - INS_OPTS_SCALABLE_D); // IF_SVE_CM_3A /* CLASTB ., , ., . */ + INS_OPTS_SCALABLE_D); /* CLASTB ., , ., . */ + // IF_SVE_CN_3A theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15, - INS_OPTS_SCALABLE_H_TO_SIMD); // IF_SVE_CN_3A /* CLASTA , , , . - // */ + INS_OPTS_SCALABLE_H_TO_SIMD); /* CLASTA , , , . */ theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16, - INS_OPTS_SCALABLE_S_TO_SIMD); // IF_SVE_CN_3A /* CLASTB , , , . - // */ + INS_OPTS_SCALABLE_S_TO_SIMD); /* CLASTB , , , . */ + theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17, + INS_OPTS_SCALABLE_D_TO_SIMD); /* CLASTB , , , . */ + // IF_SVE_CO_3A // Note: EA_4BYTE used for B and H (destination register is W) theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0, - INS_OPTS_SCALABLE_B_TO_SCALAR); // IF_SVE_CO_3A /* CLASTA , , , - // . */ + INS_OPTS_SCALABLE_B_TO_SCALAR); /* CLASTA , , , . */ theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3, - INS_OPTS_SCALABLE_H_TO_SCALAR); // IF_SVE_CO_3A /* CLASTA , , , - // . */ + INS_OPTS_SCALABLE_H_TO_SCALAR); /* CLASTA , , , . */ theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12, - INS_OPTS_SCALABLE_S_TO_SCALAR); // IF_SVE_CO_3A /* CLASTB , , , - // . */ + INS_OPTS_SCALABLE_S_TO_SCALAR); /* CLASTB , , , . */ theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9, - INS_OPTS_SCALABLE_D_TO_SCALAR); // IF_SVE_CO_3A /* CLASTB , , , - // . */ + INS_OPTS_SCALABLE_D_TO_SCALAR); /* CLASTB , , , . */ + // IF_SVE_EP_3A theEmitter->emitIns_R_R_R(INS_sve_shadd, EA_SCALABLE, REG_V15, REG_P0, REG_V10, - INS_OPTS_SCALABLE_B); // IF_SVE_EP_3A /* SHADD ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* SHADD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_shsub, EA_SCALABLE, REG_V16, REG_P1, REG_V11, - INS_OPTS_SCALABLE_H); // IF_SVE_EP_3A /* SHSUB ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* SHSUB ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_shsubr, EA_SCALABLE, REG_V17, REG_P2, REG_V12, - INS_OPTS_SCALABLE_S); // IF_SVE_EP_3A /* SHSUBR ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* SHSUBR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_srhadd, EA_SCALABLE, REG_V18, REG_P3, REG_V13, - INS_OPTS_SCALABLE_D); // IF_SVE_EP_3A /* SRHADD ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* SRHADD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uhadd, EA_SCALABLE, REG_V19, REG_P4, REG_V14, - INS_OPTS_SCALABLE_B); // IF_SVE_EP_3A /* UHADD ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* UHADD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uhsub, EA_SCALABLE, REG_V20, REG_P5, REG_V15, - INS_OPTS_SCALABLE_H); // IF_SVE_EP_3A /* UHSUB ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* UHSUB ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uhsubr, EA_SCALABLE, REG_V21, REG_P6, REG_V16, - INS_OPTS_SCALABLE_S); // IF_SVE_EP_3A /* UHSUBR ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* UHSUBR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_urhadd, EA_SCALABLE, REG_V22, REG_P7, REG_V17, - INS_OPTS_SCALABLE_D); // IF_SVE_EP_3A /* URHADD ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* URHADD ., /M, ., . */ + // IF_SVE_ER_3A theEmitter->emitIns_R_R_R(INS_sve_addp, EA_SCALABLE, REG_V23, REG_P6, REG_V18, - INS_OPTS_SCALABLE_B); // IF_SVE_ER_3A /* ADDP ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* ADDP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_smaxp, EA_SCALABLE, REG_V24, REG_P5, REG_V19, - INS_OPTS_SCALABLE_H); // IF_SVE_ER_3A /* SMAXP ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* SMAXP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_sminp, EA_SCALABLE, REG_V25, REG_P4, REG_V20, - INS_OPTS_SCALABLE_S); // IF_SVE_ER_3A /* SMINP ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* SMINP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_umaxp, EA_SCALABLE, REG_V26, REG_P3, REG_V21, - INS_OPTS_SCALABLE_D); // IF_SVE_ER_3A /* UMAXP ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* UMAXP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uminp, EA_SCALABLE, REG_V27, REG_P2, REG_V22, - INS_OPTS_SCALABLE_B); // IF_SVE_ER_3A /* UMINP ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* UMINP ., /M, ., . */ + // IF_SVE_ET_3A theEmitter->emitIns_R_R_R(INS_sve_sqadd, EA_SCALABLE, REG_V28, REG_P1, REG_V23, - INS_OPTS_SCALABLE_B); // IF_SVE_ET_3A /* SQADD ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* SQADD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_sqsub, EA_SCALABLE, REG_V29, REG_P0, REG_V24, - INS_OPTS_SCALABLE_H); // IF_SVE_ET_3A /* SQSUB ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* SQSUB ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_sqsubr, EA_SCALABLE, REG_V30, REG_P1, REG_V25, - INS_OPTS_SCALABLE_H); // IF_SVE_ET_3A /* SQSUBR ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* SQSUBR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_suqadd, EA_SCALABLE, REG_V31, REG_P2, REG_V26, - INS_OPTS_SCALABLE_B); // IF_SVE_ET_3A /* SUQADD ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* SUQADD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqadd, EA_SCALABLE, REG_V0, REG_P3, REG_V27, - INS_OPTS_SCALABLE_S); // IF_SVE_ET_3A /* UQADD ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* UQADD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqsub, EA_SCALABLE, REG_V1, REG_P4, REG_V28, - INS_OPTS_SCALABLE_D); // IF_SVE_ET_3A /* UQSUB ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* UQSUB ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqsubr, EA_SCALABLE, REG_V2, REG_P5, REG_V29, - INS_OPTS_SCALABLE_B); // IF_SVE_ET_3A /* UQSUBR ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* UQSUBR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_usqadd, EA_SCALABLE, REG_V3, REG_P6, REG_V30, - INS_OPTS_SCALABLE_B); // IF_SVE_ET_3A /* USQADD ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* USQADD ., /M, ., . */ + // IF_SVE_EU_3A theEmitter->emitIns_R_R_R(INS_sve_sqrshl, EA_SCALABLE, REG_V4, REG_P7, REG_V31, - INS_OPTS_SCALABLE_B); // IF_SVE_EU_3A /* SQRSHL ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* SQRSHL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_sqrshlr, EA_SCALABLE, REG_V5, REG_P0, REG_V30, - INS_OPTS_SCALABLE_H); // IF_SVE_EU_3A /* SQRSHLR ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* SQRSHLR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_sqshl, EA_SCALABLE, REG_V6, REG_P1, REG_V29, - INS_OPTS_SCALABLE_S); // IF_SVE_EU_3A /* SQSHL ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* SQSHL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_sqshlr, EA_SCALABLE, REG_V7, REG_P2, REG_V28, - INS_OPTS_SCALABLE_D); // IF_SVE_EU_3A /* SQSHLR ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* SQSHLR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_srshl, EA_SCALABLE, REG_V8, REG_P3, REG_V27, - INS_OPTS_SCALABLE_B); // IF_SVE_EU_3A /* SRSHL ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* SRSHL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_srshlr, EA_SCALABLE, REG_V9, REG_P4, REG_V26, - INS_OPTS_SCALABLE_H); // IF_SVE_EU_3A /* SRSHLR ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* SRSHLR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqrshl, EA_SCALABLE, REG_V10, REG_P5, REG_V25, - INS_OPTS_SCALABLE_S); // IF_SVE_EU_3A /* UQRSHL ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* UQRSHL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqrshlr, EA_SCALABLE, REG_V11, REG_P6, REG_V24, - INS_OPTS_SCALABLE_D); // IF_SVE_EU_3A /* UQRSHLR ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* UQRSHLR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqshl, EA_SCALABLE, REG_V12, REG_P7, REG_V23, - INS_OPTS_SCALABLE_B); // IF_SVE_EU_3A /* UQSHL ., /M, ., . */ + INS_OPTS_SCALABLE_B); /* UQSHL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_uqshlr, EA_SCALABLE, REG_V13, REG_P0, REG_V22, - INS_OPTS_SCALABLE_H); // IF_SVE_EU_3A /* UQSHLR ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* UQSHLR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_urshl, EA_SCALABLE, REG_V14, REG_P1, REG_V21, - INS_OPTS_SCALABLE_S); // IF_SVE_EU_3A /* URSHL ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* URSHL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_urshlr, EA_SCALABLE, REG_V15, REG_P2, REG_V20, - INS_OPTS_SCALABLE_D); // IF_SVE_EU_3A /* URSHLR ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* URSHLR ., /M, ., . */ + // IF_SVE_GR_3A theEmitter->emitIns_R_R_R(INS_sve_faddp, EA_SCALABLE, REG_V16, REG_P3, REG_V19, - INS_OPTS_SCALABLE_H); // IF_SVE_GR_3A /* FADDP ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* FADDP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmaxnmp, EA_SCALABLE, REG_V17, REG_P4, REG_V18, - INS_OPTS_SCALABLE_S); // IF_SVE_GR_3A /* FMAXNMP ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FMAXNMP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmaxp, EA_SCALABLE, REG_V18, REG_P5, REG_V17, - INS_OPTS_SCALABLE_D); // IF_SVE_GR_3A /* FMAXP ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* FMAXP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fminnmp, EA_SCALABLE, REG_V19, REG_P6, REG_V16, - INS_OPTS_SCALABLE_S); // IF_SVE_GR_3A /* FMINNMP ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FMINNMP ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fminp, EA_SCALABLE, REG_V20, REG_P7, REG_V15, - INS_OPTS_SCALABLE_H); // IF_SVE_GR_3A /* FMINP ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* FMINP ., /M, ., . */ + // IF_SVE_HJ_3A theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14, - INS_OPTS_SCALABLE_H_TO_SIMD); // IF_SVE_HJ_3A /* FADDA , , , . - // */ + INS_OPTS_SCALABLE_H_TO_SIMD); /* FADDA , , , . */ theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13, - INS_OPTS_SCALABLE_S_TO_SIMD); // IF_SVE_HJ_3A /* FADDA , , , . - // */ + INS_OPTS_SCALABLE_S_TO_SIMD); /* FADDA , , , . */ theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12, - INS_OPTS_SCALABLE_D_TO_SIMD); // IF_SVE_HJ_3A /* FADDA , , , . - // */ - + INS_OPTS_SCALABLE_D_TO_SIMD); /* FADDA , , , . */ + // IF_SVE_HL_3A theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11, - INS_OPTS_SCALABLE_H); // IF_SVE_HL_3A /* FABD ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* FABD ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fadd, EA_SCALABLE, REG_V25, REG_P2, REG_V10, - INS_OPTS_SCALABLE_S); // IF_SVE_HL_3A /* FADD ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FADD ., /M, ., . */ // These are not yet supported by capstone. - // theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D); // - // IF_SVE_HL_3A /* FAMAX ., /M, ., . */ - // theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H); // - // IF_SVE_HL_3A /* FAMIN ., /M, ., . */ + // theEmitter->emitIns_R_R_R(INS_sve_famax, EA_SCALABLE, REG_V26, REG_P1, REG_V9, INS_OPTS_SCALABLE_D); + /* FAMAX ., /M, ., . */ + // theEmitter->emitIns_R_R_R(INS_sve_famin, EA_SCALABLE, REG_V27, REG_P0, REG_V8, INS_OPTS_SCALABLE_H); + /* FAMIN ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fdiv, EA_SCALABLE, REG_V28, REG_P0, REG_V7, - INS_OPTS_SCALABLE_S); // IF_SVE_HL_3A /* FDIV ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FDIV ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fdivr, EA_SCALABLE, REG_V29, REG_P1, REG_V6, - INS_OPTS_SCALABLE_D); // IF_SVE_HL_3A /* FDIVR ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* FDIVR ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmax, EA_SCALABLE, REG_V30, REG_P2, REG_V5, - INS_OPTS_SCALABLE_H); // IF_SVE_HL_3A /* FMAX ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* FMAX ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmaxnm, EA_SCALABLE, REG_V31, REG_P3, REG_V4, - INS_OPTS_SCALABLE_S); // IF_SVE_HL_3A /* FMAXNM ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FMAXNM ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmin, EA_SCALABLE, REG_V0, REG_P4, REG_V3, - INS_OPTS_SCALABLE_D); // IF_SVE_HL_3A /* FMIN ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* FMIN ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fminnm, EA_SCALABLE, REG_V1, REG_P5, REG_V2, - INS_OPTS_SCALABLE_H); // IF_SVE_HL_3A /* FMINNM ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* FMINNM ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmul, EA_SCALABLE, REG_V2, REG_P6, REG_V1, - INS_OPTS_SCALABLE_S); // IF_SVE_HL_3A /* FMUL ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FMUL ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fmulx, EA_SCALABLE, REG_V3, REG_P7, REG_V0, - INS_OPTS_SCALABLE_D); // IF_SVE_HL_3A /* FMULX ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* FMULX ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fscale, EA_SCALABLE, REG_V4, REG_P6, REG_V31, - INS_OPTS_SCALABLE_H); // IF_SVE_HL_3A /* FSCALE ., /M, ., . */ + INS_OPTS_SCALABLE_H); /* FSCALE ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fsub, EA_SCALABLE, REG_V5, REG_P5, REG_V30, - INS_OPTS_SCALABLE_S); // IF_SVE_HL_3A /* FSUB ., /M, ., . */ + INS_OPTS_SCALABLE_S); /* FSUB ., /M, ., . */ theEmitter->emitIns_R_R_R(INS_sve_fsubr, EA_SCALABLE, REG_V6, REG_P4, REG_V29, - INS_OPTS_SCALABLE_D); // IF_SVE_HL_3A /* FSUBR ., /M, ., . */ + INS_OPTS_SCALABLE_D); /* FSUBR ., /M, ., . */ #endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE diff --git a/src/coreclr/jit/emitarm64.cpp b/src/coreclr/jit/emitarm64.cpp index 228e6d4dabdde..fe3c9231bb720 100644 --- a/src/coreclr/jit/emitarm64.cpp +++ b/src/coreclr/jit/emitarm64.cpp @@ -943,6 +943,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(datasize == EA_8BYTE); break; + // Scalable. case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated) case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) case IF_SVE_AD_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer min/max/difference (predicated) @@ -962,6 +963,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(isScalableVectorSize(elemsize)); break; + // Scalable, .S or .D. case IF_SVE_AC_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated) elemsize = id->idOpSize(); assert(insOptsScalableWords(id->idInsOpt())); // xx @@ -971,6 +973,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(isScalableVectorSize(elemsize)); break; + // Scalable Wide. case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated) elemsize = id->idOpSize(); assert(insOptsScalableWide(id->idInsOpt())); // xx @@ -980,16 +983,27 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(isScalableVectorSize(elemsize)); break; + // Scalable to Simd. case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar - case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) elemsize = id->idOpSize(); assert(insOptsScalableToSimd(id->idInsOpt())); // xx assert(isVectorRegister(id->idReg1())); // ddddd assert(isLowPredicateRegister(id->idReg2())); // ggg assert(isVectorRegister(id->idReg3())); // mmmmm + assert(isValidVectorElemsize(elemsize)); + break; + + // Scalable to FP Simd. + case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) + elemsize = id->idOpSize(); + assert(insOptsScalableToSimdFloat(id->idInsOpt())); // xx + assert(isVectorRegister(id->idReg1())); // ddddd + assert(isLowPredicateRegister(id->idReg2())); // ggg + assert(isVectorRegister(id->idReg3())); // mmmmm assert(isValidVectorElemsizeSveFloat(elemsize)); break; + // Scalable to general register. case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register elemsize = id->idOpSize(); assert(insOptsScalableToScalar(id->idInsOpt())); // xx @@ -999,6 +1013,7 @@ void emitter::emitInsSanityCheck(instrDesc* id) assert(isValidScalarDatasize(elemsize)); break; + // Scalable FP. case IF_SVE_GR_3A: // ........xx...... ...gggmmmmmddddd -- SVE2 floating-point pairwise operations case IF_SVE_HL_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point arithmetic (predicated) elemsize = id->idOpSize(); @@ -13920,6 +13935,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) dst += emitOutput_Instr(dst, code); break; + // Scalable. case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated) case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) case IF_SVE_AC_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated) @@ -13945,6 +13961,7 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp) dst += emitOutput_Instr(dst, code); break; + // Scalable to general register. case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register code = emitInsCodeSve(ins, fmt); code |= insEncodeReg_Rd(id->idReg1()); // ddddd @@ -16145,6 +16162,7 @@ void emitter::emitDispInsHelp( } break; + // Scalable. case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated) case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) case IF_SVE_AC_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated) @@ -16164,6 +16182,7 @@ void emitter::emitDispInsHelp( emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; + // Scalable. Reg3 is .D. case IF_SVE_AO_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise shift by wide elements (predicated) emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd emitDispPredicateReg(id->idReg2(), PREDICATE_MERGE, true); // ggg @@ -16171,6 +16190,7 @@ void emitter::emitDispInsHelp( emitDispSveReg(id->idReg3(), INS_OPTS_SCALABLE_D, false); // mmmmm break; + // Scalable. No predicate type. case IF_SVE_CM_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally broadcast element to vector emitDispSveReg(id->idReg1(), id->idInsOpt(), true); // ddddd emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg @@ -16178,20 +16198,9 @@ void emitter::emitDispInsHelp( emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm break; + // Scalable to general register or SIMD. No predicate type. case IF_SVE_CN_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to SIMD&FP scalar - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm - break; - case IF_SVE_CO_3A: // ........xx...... ...gggmmmmmddddd -- SVE conditionally extract element to general register - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg - emitDispReg(id->idReg1(), size, true); // ddddd - emitDispSveReg(id->idReg3(), id->idInsOpt(), false); // mmmmm - break; - case IF_SVE_HJ_3A: // ........xx...... ...gggmmmmmddddd -- SVE floating-point serial reduction (predicated) emitDispReg(id->idReg1(), size, true); // ddddd emitDispPredicateReg(id->idReg2(), PREDICATE_NONE, true); // ggg @@ -18384,6 +18393,7 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins } break; + // Scalable. case IF_SVE_AA_3A: // ........xx...... ...gggmmmmmddddd -- SVE bitwise logical operations (predicated) case IF_SVE_AB_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer add/subtract vectors (predicated) case IF_SVE_AC_3A: // ........xx...... ...gggmmmmmddddd -- SVE integer divide vectors (predicated) diff --git a/src/coreclr/jit/emitarm64.h b/src/coreclr/jit/emitarm64.h index 441ed8b2d7b24..0926a95abb5bb 100644 --- a/src/coreclr/jit/emitarm64.h +++ b/src/coreclr/jit/emitarm64.h @@ -876,8 +876,7 @@ inline static bool insOptsScalableWords(insOpts opt) inline static bool insOptsScalableFloat(insOpts opt) { // Opt is any of the standard scalable types that are valid for FP. - return ((opt == INS_OPTS_SCALABLE_B) || (opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S) || - (opt == INS_OPTS_SCALABLE_D)); + return ((opt == INS_OPTS_SCALABLE_H) || (opt == INS_OPTS_SCALABLE_S) || (opt == INS_OPTS_SCALABLE_D)); } inline static bool insOptsScalableWide(insOpts opt)