[RyuJit/WASM] Reach the NYI in genFnProlog (#121863)

Pulling on the thread of NYIs a bit further. We now have this for my
`Problem(int a, int b) => a + b;`:
```cs
Scope info: begin block BB01, IL range [000..004)
Added IP mapping: 0x0000 STACK_EMPTY (G_M56520_IG02,ins#0,ofs#0) label
Generating:                [000004] -----------                            IL_OFFSET void   INLRT @ 0x000[E--]
Generating: N001 (  1,  1) [000000] -----+-----                    t0 =    LCL_VAR   int    V00 arg0         u:1 (last use) $80
Mapped BB01 to G_M56520_IG02
IN0001:             i32.load 1 4
Debug: Closing V00 debug range.
                                                        Live vars after [000000]: {V00 V01} -{V00} => {V01}
Generating: N002 (  1,  1) [000001] -----+-----                    t1 =    LCL_VAR   int    V01 arg1         u:1 (last use) $81
IN0002:             i32.load 1 0
Debug: Closing V01 debug range.
                                                        Live vars after [000001]: {V01} -{V01} => {}
                                                                        /--*  t0     int
                                                                        +--*  t1     int
Generating: N003 (  3,  3) [000002] -----+-----                    t2 = *  ADD       int    $100
IN0003:             i32.add
                                                                        /--*  t2     int
Generating: N004 (  4,  4) [000003] -----+-----                         *  RETURN    int    $VN.Void
```

Author: SingleAccretion

src/coreclr/jit/codegenarmarch.cpp

@@ -3183,7 +3183,7 @@ void CodeGen::genCall(GenTreeCall* call)
 #ifdef TARGET_ARM
                 if (compiler->opts.compUseSoftFP && returnType == TYP_DOUBLE)
                 {
-                    inst_RV_RV_RV(INS_vmov_i2d, call->GetRegNum(), returnReg, genRegArgNext(returnReg), EA_8BYTE);
+                    inst_RV_RV_RV(INS_vmov_i2d, call->GetRegNum(), returnReg, REG_NEXT(returnReg), EA_8BYTE);
                 }
                 else if (compiler->opts.compUseSoftFP && returnType == TYP_FLOAT)
                 {

src/coreclr/jit/codegencommon.cpp

@@ -6949,6 +6949,7 @@ void CodeGen::genLongReturn(GenTree* treeNode)
     inst_Mov(targetType, REG_LNGRET_HI, hiRetVal->GetRegNum(), /* canSkip */ true, emitActualTypeSize(TYP_INT));
 }
 #endif // TARGET_X86 || TARGET_ARM
+#endif // !TARGET_WASM
 
 //------------------------------------------------------------------------
 // genReturn: Generates code for return statement.
@@ -6995,7 +6996,7 @@ void CodeGen::genReturn(GenTree* treeNode)
         else if (targetType != TYP_VOID)
         {
             assert(op1 != nullptr);
-            noway_assert(op1->GetRegNum() != REG_NA);
+            noway_assert(!HAS_FIXED_REGISTER_SET || (op1->GetRegNum() != REG_NA));
 
             // !! NOTE !! genConsumeReg will clear op1 as GC ref after it has
             // consumed a reg for the operand. This is because the variable
@@ -7005,6 +7006,7 @@ void CodeGen::genReturn(GenTree* treeNode)
             // instructions until emitted then should not rely on the outdated GC info.
             genConsumeReg(op1);
 
+#if HAS_FIXED_REGISTER_SET
 #if defined(TARGET_ARM64) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
             genSimpleReturn(treeNode);
 #else // !TARGET_ARM64 || !TARGET_LOONGARCH64 || !TARGET_RISCV64
@@ -7047,6 +7049,7 @@ void CodeGen::genReturn(GenTree* treeNode)
                 inst_Mov_Extend(targetType, /* srcInReg */ true, retReg, op1->GetRegNum(), /* canSkip */ true);
             }
 #endif // !TARGET_ARM64 || !TARGET_LOONGARCH64 || !TARGET_RISCV64
+#endif // HAS_FIXED_REGISTER_SET
         }
     }
 
@@ -7055,10 +7058,12 @@ void CodeGen::genReturn(GenTree* treeNode)
         instGen_Set_Reg_To_Zero(EA_PTRSIZE, REG_ASYNC_CONTINUATION_RET);
     }
 
+#if EMIT_GENERATE_GCINFO
     if (treeNode->OperIs(GT_RETURN, GT_SWIFT_ERROR_RET))
     {
         genMarkReturnGCInfo();
     }
+#endif // EMIT_GENERATE_GCINFO
 
 #ifdef PROFILING_SUPPORTED
 
@@ -7103,6 +7108,7 @@ void CodeGen::genReturn(GenTree* treeNode)
 #endif // defined(DEBUG) && defined(TARGET_XARCH)
 }
 
+#ifndef TARGET_WASM
 #ifdef SWIFT_SUPPORT
 //------------------------------------------------------------------------
 // genSwiftErrorReturn: Generates code for returning the normal return value,
@@ -7200,6 +7206,7 @@ void CodeGen::genCodeForAsyncContinuation(GenTree* tree)
 
     genProduceReg(tree);
 }
+#endif // !TARGET_WASM
 
 //------------------------------------------------------------------------
 // isStructReturn: Returns whether the 'treeNode' is returning a struct.
@@ -7234,6 +7241,7 @@ bool CodeGen::isStructReturn(GenTree* treeNode)
 #endif
 }
 
+#ifndef TARGET_WASM
 //------------------------------------------------------------------------
 // genStructReturn: Generates code for returning a struct.
 //

src/coreclr/jit/codegenlinear.cpp

@@ -1062,6 +1062,7 @@ void CodeGenInterface::genUpdateVarReg(LclVarDsc* varDsc, GenTree* tree, int reg
     assert(tree->IsMultiRegLclVar() || tree->OperIs(GT_COPY));
     varDsc->SetRegNum(tree->GetRegByIndex(regIndex));
 }
+#endif // !TARGET_WASM
 
 //------------------------------------------------------------------------
 // genUpdateVarReg: Update the current register location for a lclVar
@@ -1078,6 +1079,7 @@ void CodeGenInterface::genUpdateVarReg(LclVarDsc* varDsc, GenTree* tree)
     varDsc->SetRegNum(tree->GetRegNum());
 }
 
+#ifndef TARGET_WASM
 //------------------------------------------------------------------------
 // genUnspillLocal: Reload a register candidate local into a register, if needed.
 //
@@ -1610,7 +1612,6 @@ regNumber CodeGen::genConsumeReg(GenTree* tree)
     return tree->GetRegNum();
 }
 
-#ifndef TARGET_WASM
 // Do liveness update for an address tree: one of GT_LEA, GT_LCL_VAR, or GT_CNS_INT (for call indirect).
 void CodeGen::genConsumeAddress(GenTree* addr)
 {
@@ -1763,6 +1764,7 @@ void CodeGen::genConsumeOperands(GenTreeOp* tree)
     }
 }
 
+#ifndef TARGET_WASM
 #if defined(FEATURE_SIMD) || defined(FEATURE_HW_INTRINSICS)
 //------------------------------------------------------------------------
 // genConsumeOperands: Do liveness update for the operands of a multi-operand node,
@@ -2087,6 +2089,7 @@ void CodeGen::genSpillLocal(unsigned varNum, var_types type, GenTreeLclVar* lclN
                                   varNum, 0);
     }
 }
+#endif // !TARGET_WASM
 
 //-------------------------------------------------------------------------
 // genProduceReg: do liveness update for register produced by the current
@@ -2105,6 +2108,7 @@ void CodeGen::genProduceReg(GenTree* tree)
     tree->gtDebugFlags |= GTF_DEBUG_NODE_CG_PRODUCED;
 #endif
 
+#if HAS_FIXED_REGISTER_SET
     if (tree->gtFlags & GTF_SPILL)
     {
         // Code for GT_COPY node gets generated as part of consuming regs by its parent.
@@ -2174,10 +2178,12 @@ void CodeGen::genProduceReg(GenTree* tree)
             return;
         }
     }
+#endif // HAS_FIXED_REGISTER_SET
 
     // Updating variable liveness after instruction was emitted
     genUpdateLife(tree);
 
+#if EMIT_GENERATE_GCINFO
     // If we've produced a register, mark it as a pointer, as needed.
     if (tree->gtHasReg(compiler))
     {
@@ -2254,8 +2260,10 @@ void CodeGen::genProduceReg(GenTree* tree)
             }
         }
     }
+#endif // EMIT_GENERATE_GCINFO
 }
 
+#ifndef TARGET_WASM
 // transfer gc/byref status of src reg to dst reg
 void CodeGen::genTransferRegGCState(regNumber dst, regNumber src)
 {

src/coreclr/jit/codegenwasm.cpp

@@ -59,9 +59,110 @@ void CodeGen::genFuncletEpilog()
     NYI_WASM("genFuncletEpilog");
 }
 
-void CodeGen::genCodeForTreeNode(GenTree* node)
+void CodeGen::genCodeForTreeNode(GenTree* treeNode)
 {
-    NYI_WASM("genCodeForTreeNode");
+#ifdef DEBUG
+    lastConsumedNode = nullptr;
+    if (compiler->verbose)
+    {
+        compiler->gtDispLIRNode(treeNode, "Generating: ");
+    }
+#endif // DEBUG
+
+    assert(!treeNode->IsReuseRegVal()); // TODO-WASM-CQ: enable.
+
+    // Contained nodes are part of the parent for codegen purposes.
+    if (treeNode->isContained())
+    {
+        return;
+    }
+
+    switch (treeNode->OperGet())
+    {
+        case GT_ADD:
+            genCodeForBinary(treeNode->AsOp());
+            break;
+
+        case GT_LCL_VAR:
+            genCodeForLclVar(treeNode->AsLclVar());
+            break;
+
+        case GT_RETURN:
+            genReturn(treeNode);
+            break;
+
+        case GT_IL_OFFSET:
+            // Do nothing; this node is a marker for debug info.
+            break;
+
+        default:
+#ifdef DEBUG
+            NYIRAW(GenTree::OpName(treeNode->OperGet()));
+#else
+            NYI_WASM("Opcode not implemented");
+#endif
+            break;
+    }
+}
+
+//------------------------------------------------------------------------
+// genCodeForBinary: Generate code for a binary arithmetic operator
+//
+// Arguments:
+//    treeNode - The binary operation for which we are generating code.
+//
+void CodeGen::genCodeForBinary(GenTreeOp* treeNode)
+{
+    genConsumeOperands(treeNode);
+
+    instruction ins;
+    switch (treeNode->OperGet())
+    {
+        case GT_ADD:
+            if (!treeNode->TypeIs(TYP_INT))
+            {
+                NYI_WASM("genCodeForBinary: non-INT GT_ADD");
+            }
+            ins = INS_i32_add;
+            break;
+        default:
+            ins = INS_none;
+            NYI_WASM("genCodeForBinary");
+            break;
+    }
+
+    GetEmitter()->emitIns(ins);
+    genProduceReg(treeNode);
+}
+
+//------------------------------------------------------------------------
+// genCodeForLclVar: Produce code for a GT_LCL_VAR node.
+//
+// Arguments:
+//    tree - the GT_LCL_VAR node
+//
+void CodeGen::genCodeForLclVar(GenTreeLclVar* tree)
+{
+    assert(tree->OperIs(GT_LCL_VAR) && !tree->IsMultiReg());
+    LclVarDsc* varDsc = compiler->lvaGetDesc(tree);
+
+    // Unlike other targets, we can't "reload at the point of use", since that would require inserting instructions
+    // into the middle of an already-emitted instruction group. Instead, we order the nodes in a way that obeys the
+    // value stack constraints of WASM precisely. However, the liveness tracking is done in the same way as for other
+    // targets, hence "genProduceReg" is only called for non-candidates.
+    if (!varDsc->lvIsRegCandidate())
+    {
+        var_types type = varDsc->GetRegisterType(tree);
+        // TODO-WASM: actually local.get the frame base local here.
+        GetEmitter()->emitIns_S(ins_Load(type), emitTypeSize(tree), tree->GetLclNum(), 0);
+        genProduceReg(tree);
+    }
+    else
+    {
+        assert(genIsValidReg(varDsc->GetRegNum()));
+        unsigned wasmLclIndex = UnpackWasmReg(varDsc->GetRegNum());
+        GetEmitter()->emitIns_I(INS_local_get, emitTypeSize(tree), wasmLclIndex);
+    }
 }
 
 BasicBlock* CodeGen::genCallFinally(BasicBlock* block)
@@ -76,13 +177,23 @@ void CodeGen::genEHCatchRet(BasicBlock* block)
     NYI_WASM("genEHCatchRet");
 }
 
+void CodeGen::genStructReturn(GenTree* treeNode)
+{
+    NYI_WASM("genStructReturn");
+}
+
 void CodeGen::genEmitGSCookieCheck(bool tailCall)
 {
     // TODO-WASM: GS cookie checks have limited utility on WASM since they can only help
     // with detecting linear memory stack corruption. Decide if we want them anyway.
     NYI_WASM("genEmitGSCookieCheck");
 }
 
+void CodeGen::genProfilingLeaveCallback(unsigned helper)
+{
+    NYI_WASM("genProfilingLeaveCallback");
+}
+
 void CodeGen::genSpillVar(GenTree* tree)
 {
     NYI_WASM("Put all spillng to memory under '#if HAS_FIXED_REGISTER_SET'");
@@ -159,11 +270,6 @@ void CodeGenInterface::genUpdateVarReg(LclVarDsc* varDsc, GenTree* tree, int reg
     NYI_WASM("Move genUpdateVarReg from codegenlinear.cpp to codegencommon.cpp shared code");
 }
 
-void CodeGenInterface::genUpdateVarReg(LclVarDsc* varDsc, GenTree* tree)
-{
-    NYI_WASM("Move genUpdateVarReg from codegenlinear.cpp to codegencommon.cpp shared code");
-}
-
 void RegSet::verifyRegUsed(regNumber reg)
 {
 }

src/coreclr/jit/emit.cpp

@@ -1357,10 +1357,6 @@ void emitter::emitBegFN(bool hasFramePtr
     ig->igPrev          = nullptr;
 #endif
 
-#ifdef DEBUG
-    emitScratchSigInfo = nullptr;
-#endif // DEBUG
-
     /* Append another group, to start generating the method body */
 
     emitNewIG();
@@ -10102,7 +10098,7 @@ void emitter::emitRemoveLastInstruction()
  *  emitGetInsSC: Get the instruction's constant value.
  */
 
-cnsval_ssize_t emitter::emitGetInsSC(const instrDesc* id) const
+cnsval_ssize_t emitter::emitGetInsSC(const instrDesc* id)
 {
 #ifdef TARGET_ARM // should it be TARGET_ARMARCH? Why do we need this? Note that on ARM64 we store scaled immediates
                   // for some formats

src/coreclr/jit/emit.h

@@ -1264,12 +1264,7 @@ class emitter
             _idCodeSize = sz;
         }
 #elif defined(TARGET_WASM)
-        unsigned idCodeSize() const
-        {
-            // TODO-WASM: return an accurate number here based on instruction format/opcode like ARM64 above.
-            NYI_WASM("isCodeSize");
-            return 0;
-        }
+        unsigned idCodeSize() const;
 #endif
 
         emitAttr idOpSize() const
@@ -2460,8 +2455,8 @@ class emitter
     static bool          HasApxPpx(instruction ins);
 #endif // TARGET_XARCH
 
-    cnsval_ssize_t emitGetInsSC(const instrDesc* id) const;
-    unsigned       emitInsCount;
+    NOT_ARM(static) cnsval_ssize_t emitGetInsSC(const instrDesc* id);
+    unsigned emitInsCount;
 
     /************************************************************************/
     /*           A few routines used for debug display purposes             */
@@ -3623,12 +3618,6 @@ class emitter
                             CORINFO_SIG_INFO*     callSig,       /* IN */
                             CORINFO_METHOD_HANDLE methodHandle); /* IN */
 
-#ifdef DEBUG
-    // This is a scratch buffer used to minimize the number of sig info structs
-    // we have to allocate for recordCallSite.
-    CORINFO_SIG_INFO* emitScratchSigInfo;
-#endif // DEBUG
-
     /************************************************************************/
     /*               Logic to collect and display statistics                */
     /************************************************************************/

src/coreclr/jit/emitfmtswasm.h

@@ -26,7 +26,10 @@ enum ID_OPS
 //                  (unused)
 //////////////////////////////////////////////////////////////////////////////
 
-IF_DEF(NONE, IS_NONE, NONE)
+IF_DEF(NONE,    IS_NONE, NONE)
+IF_DEF(OPCODE,  IS_NONE, NONE) // <opcode>
+IF_DEF(ULEB128, IS_NONE, NONE) // <opcode> <ULEB128 immediate>
+IF_DEF(MEMARG,  IS_NONE, NONE) // <opcode> <memarg> (<align> <offset>)
 
 #undef IF_DEF
 #endif // !DEFINE_ID_OPS