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kunalspathakkunalspathak
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Arm64/Sve: Do not mark *Prefetch* APIs as MEMORY_LOAD (#104396)
* fix prefetch in proper way * jit format * review comment
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5 files changed

+108
-40
lines changed

5 files changed

+108
-40
lines changed

‎src/coreclr/jit/fgdiagnostic.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3459,6 +3459,14 @@ void Compiler::fgDebugCheckFlags(GenTree* tree, BasicBlock* block)
34593459

34603460
#if defined(TARGET_ARM64)
34613461
case NI_ArmBase_Yield:
3462+
case NI_Sve_PrefetchBytes:
3463+
case NI_Sve_PrefetchInt16:
3464+
case NI_Sve_PrefetchInt32:
3465+
case NI_Sve_PrefetchInt64:
3466+
case NI_Sve_GatherPrefetch16Bit:
3467+
case NI_Sve_GatherPrefetch32Bit:
3468+
case NI_Sve_GatherPrefetch64Bit:
3469+
case NI_Sve_GatherPrefetch8Bit:
34623470
{
34633471
assert(tree->OperRequiresCallFlag(this));
34643472
expectedFlags |= GTF_GLOB_REF;

‎src/coreclr/jit/gentree.cpp‎

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -27459,17 +27459,9 @@ bool GenTreeHWIntrinsic::OperIsMemoryLoad(GenTree** pAddr) const
2745927459
case NI_Sve_Load2xVectorAndUnzip:
2746027460
case NI_Sve_Load3xVectorAndUnzip:
2746127461
case NI_Sve_Load4xVectorAndUnzip:
27462-
case NI_Sve_PrefetchBytes:
27463-
case NI_Sve_PrefetchInt16:
27464-
case NI_Sve_PrefetchInt32:
27465-
case NI_Sve_PrefetchInt64:
2746627462
addr = Op(2);
2746727463
break;
2746827464

27469-
case NI_Sve_GatherPrefetch8Bit:
27470-
case NI_Sve_GatherPrefetch16Bit:
27471-
case NI_Sve_GatherPrefetch32Bit:
27472-
case NI_Sve_GatherPrefetch64Bit:
2747327465
case NI_Sve_GatherVector:
2747427466
case NI_Sve_GatherVectorByteZeroExtend:
2747527467
case NI_Sve_GatherVectorInt16SignExtend:
@@ -27963,6 +27955,14 @@ bool GenTreeHWIntrinsic::OperRequiresCallFlag() const
2796327955

2796427956
#if defined(TARGET_ARM64)
2796527957
case NI_ArmBase_Yield:
27958+
case NI_Sve_PrefetchBytes:
27959+
case NI_Sve_PrefetchInt16:
27960+
case NI_Sve_PrefetchInt32:
27961+
case NI_Sve_PrefetchInt64:
27962+
case NI_Sve_GatherPrefetch16Bit:
27963+
case NI_Sve_GatherPrefetch32Bit:
27964+
case NI_Sve_GatherPrefetch64Bit:
27965+
case NI_Sve_GatherPrefetch8Bit:
2796627966
{
2796727967
return true;
2796827968
}
@@ -28145,6 +28145,14 @@ void GenTreeHWIntrinsic::Initialize(NamedIntrinsic intrinsicId)
2814528145

2814628146
#if defined(TARGET_ARM64)
2814728147
case NI_ArmBase_Yield:
28148+
case NI_Sve_PrefetchBytes:
28149+
case NI_Sve_PrefetchInt16:
28150+
case NI_Sve_PrefetchInt32:
28151+
case NI_Sve_PrefetchInt64:
28152+
case NI_Sve_GatherPrefetch16Bit:
28153+
case NI_Sve_GatherPrefetch32Bit:
28154+
case NI_Sve_GatherPrefetch64Bit:
28155+
case NI_Sve_GatherPrefetch8Bit:
2814828156
{
2814928157
// Mark as a call and global reference, much as is done for GT_KEEPALIVE
2815028158
gtFlags |= (GTF_CALL | GTF_GLOB_REF);

‎src/coreclr/jit/hwintrinsic.cpp‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1856,14 +1856,6 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
18561856
break;
18571857

18581858
#elif defined(TARGET_ARM64)
1859-
case NI_Sve_GatherPrefetch8Bit:
1860-
case NI_Sve_GatherPrefetch16Bit:
1861-
case NI_Sve_GatherPrefetch32Bit:
1862-
case NI_Sve_GatherPrefetch64Bit:
1863-
assert(varTypeIsSIMD(op2->TypeGet()));
1864-
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op2ClsHnd));
1865-
break;
1866-
18671859
case NI_Sve_GatherVector:
18681860
case NI_Sve_GatherVectorByteZeroExtend:
18691861
case NI_Sve_GatherVectorInt16SignExtend:
@@ -1893,22 +1885,6 @@ GenTree* Compiler::impHWIntrinsic(NamedIntrinsic intrinsic,
18931885
assert(!isScalar);
18941886
retNode =
18951887
gtNewSimdHWIntrinsicNode(nodeRetType, op1, op2, op3, op4, intrinsic, simdBaseJitType, simdSize);
1896-
1897-
#if defined(TARGET_ARM64)
1898-
switch (intrinsic)
1899-
{
1900-
case NI_Sve_GatherPrefetch8Bit:
1901-
case NI_Sve_GatherPrefetch16Bit:
1902-
case NI_Sve_GatherPrefetch32Bit:
1903-
case NI_Sve_GatherPrefetch64Bit:
1904-
assert(varTypeIsSIMD(op3->TypeGet()));
1905-
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(getBaseJitTypeOfSIMDType(sigReader.op3ClsHnd));
1906-
break;
1907-
1908-
default:
1909-
break;
1910-
}
1911-
#endif
19121888
break;
19131889
}
19141890

‎src/coreclr/jit/hwintrinsicarm64.cpp‎

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2725,6 +2725,82 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
27252725
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op1BaseJitType);
27262726
break;
27272727
}
2728+
case NI_Sve_GatherPrefetch8Bit:
2729+
case NI_Sve_GatherPrefetch16Bit:
2730+
case NI_Sve_GatherPrefetch32Bit:
2731+
case NI_Sve_GatherPrefetch64Bit:
2732+
case NI_Sve_PrefetchBytes:
2733+
case NI_Sve_PrefetchInt16:
2734+
case NI_Sve_PrefetchInt32:
2735+
case NI_Sve_PrefetchInt64:
2736+
{
2737+
assert((sig->numArgs == 3) || (sig->numArgs == 4));
2738+
assert(!isScalar);
2739+
2740+
var_types argType = TYP_UNKNOWN;
2741+
CORINFO_CLASS_HANDLE argClass = NO_CLASS_HANDLE;
2742+
int immLowerBound = 0;
2743+
int immUpperBound = 0;
2744+
2745+
CORINFO_ARG_LIST_HANDLE arg1 = sig->args;
2746+
CORINFO_ARG_LIST_HANDLE arg2 = info.compCompHnd->getArgNext(arg1);
2747+
CORINFO_ARG_LIST_HANDLE arg3 = info.compCompHnd->getArgNext(arg2);
2748+
2749+
HWIntrinsicInfo::lookupImmBounds(intrinsic, simdSize, simdBaseType, 1, &immLowerBound, &immUpperBound);
2750+
2751+
if (sig->numArgs == 3)
2752+
{
2753+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
2754+
op3 = getArgForHWIntrinsic(argType, argClass);
2755+
2756+
assert(HWIntrinsicInfo::isImmOp(intrinsic, op3));
2757+
op3 = addRangeCheckIfNeeded(intrinsic, op3, mustExpand, immLowerBound, immUpperBound);
2758+
2759+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
2760+
op2 = getArgForHWIntrinsic(argType, argClass);
2761+
CorInfoType op2BaseJitType = getBaseJitTypeOfSIMDType(argClass);
2762+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
2763+
op1 = impPopStack().val;
2764+
2765+
#ifdef DEBUG
2766+
2767+
if ((intrinsic == NI_Sve_GatherPrefetch8Bit) || (intrinsic == NI_Sve_GatherPrefetch16Bit) ||
2768+
(intrinsic == NI_Sve_GatherPrefetch32Bit) || (intrinsic == NI_Sve_GatherPrefetch64Bit))
2769+
{
2770+
assert(varTypeIsSIMD(op2->TypeGet()));
2771+
}
2772+
else
2773+
{
2774+
assert(varTypeIsIntegral(op2->TypeGet()));
2775+
}
2776+
#endif
2777+
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, intrinsic, simdBaseJitType, simdSize);
2778+
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op2BaseJitType);
2779+
}
2780+
else
2781+
{
2782+
CORINFO_ARG_LIST_HANDLE arg4 = info.compCompHnd->getArgNext(arg3);
2783+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg4, &argClass)));
2784+
op4 = getArgForHWIntrinsic(argType, argClass);
2785+
2786+
assert(HWIntrinsicInfo::isImmOp(intrinsic, op4));
2787+
op3 = addRangeCheckIfNeeded(intrinsic, op4, mustExpand, immLowerBound, immUpperBound);
2788+
2789+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg3, &argClass)));
2790+
op3 = getArgForHWIntrinsic(argType, argClass);
2791+
CorInfoType op3BaseJitType = getBaseJitTypeOfSIMDType(argClass);
2792+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg2, &argClass)));
2793+
op2 = getArgForHWIntrinsic(argType, argClass);
2794+
argType = JITtype2varType(strip(info.compCompHnd->getArgType(sig, arg1, &argClass)));
2795+
op1 = impPopStack().val;
2796+
2797+
assert(varTypeIsSIMD(op3->TypeGet()));
2798+
retNode = gtNewSimdHWIntrinsicNode(retType, op1, op2, op3, op4, intrinsic, simdBaseJitType, simdSize);
2799+
retNode->AsHWIntrinsic()->SetAuxiliaryJitType(op3BaseJitType);
2800+
}
2801+
2802+
break;
2803+
}
27282804

27292805
default:
27302806
{

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