Fix riscv64 nativeaot native build

am11 · am11 · commit 4dbe95c7e6ba · 2024-12-13T13:31:31.000+02:00
diff --git a/src/coreclr/nativeaot/Runtime/AsmOffsetsVerify.cpp b/src/coreclr/nativeaot/Runtime/AsmOffsetsVerify.cpp
@@ -28,9 +28,12 @@ class AsmOffsets
     static_assert(offsetof(Array, m_Length) == offsetof(String, m_Length), "The length field of String and Array have different offsets");
     static_assert(sizeof(((Array*)0)->m_Length) == sizeof(((String*)0)->m_Length), "The length field of String and Array have different sizes");
 
+#define TO_STRING(x) #x
+#define OFFSET_STRING(cls, member) TO_STRING(offsetof(cls, member))
+
+// Macro definition
 #define PLAT_ASM_OFFSET(offset, cls, member) \
-    static_assert((offsetof(cls, member) == 0x##offset) || (offsetof(cls, member) > 0x##offset), "Bad asm offset for '" #cls "." #member "', the actual offset is smaller than 0x" #offset "."); \
-    static_assert((offsetof(cls, member) == 0x##offset) || (offsetof(cls, member) < 0x##offset), "Bad asm offset for '" #cls "." #member "', the actual offset is larger than 0x" #offset ".");
+    static_assert(offsetof(cls, member) == 0x##offset, "Bad asm offset for '" #cls "." #member "'. Actual offset: " OFFSET_STRING(cls, member));
 
 #define PLAT_ASM_SIZEOF(size,   cls        ) \
     static_assert((sizeof(cls) == 0x##size) || (sizeof(cls) > 0x##size), "Bad asm size for '" #cls "', the actual size is smaller than 0x" #size "."); \
diff --git a/src/coreclr/nativeaot/Runtime/StackFrameIterator.cpp b/src/coreclr/nativeaot/Runtime/StackFrameIterator.cpp
@@ -1,5 +1,6 @@
 // Licensed to the .NET Foundation under one or more agreements.
 // The .NET Foundation licenses this file to you under the MIT license.
+
 #include "common.h"
 #include "gcenv.h"
 #include "CommonTypes.h"
@@ -794,15 +795,11 @@ void StackFrameIterator::InternalInit(Thread * pThreadToWalk, NATIVE_CONTEXT* pC
     m_RegDisplay.pS9 = (PTR_uintptr_t)PTR_TO_REG(pCtx, S9);
     m_RegDisplay.pS10 = (PTR_uintptr_t)PTR_TO_REG(pCtx, S10);
     m_RegDisplay.pS11 = (PTR_uintptr_t)PTR_TO_REG(pCtx, S11);
-    m_RegDisplay.pFP = (PTR_uintptr_t)PTR_TO_REG(pCtx, FP);
-    m_RegDisplay.pRA = (PTR_uintptr_t)PTR_TO_REG(pCtx, RA);
-
+ 
     //
     // scratch regs
     //
     m_RegDisplay.pR0 = (PTR_uintptr_t)PTR_TO_REG(pCtx, R0);
-    m_RegDisplay.pGP = (PTR_uintptr_t)PTR_TO_REG(pCtx, GP);
-    m_RegDisplay.pTP = (PTR_uintptr_t)PTR_TO_REG(pCtx, TP);
     m_RegDisplay.pA0 = (PTR_uintptr_t)PTR_TO_REG(pCtx, A0);
     m_RegDisplay.pA1 = (PTR_uintptr_t)PTR_TO_REG(pCtx, A1);
     m_RegDisplay.pA2 = (PTR_uintptr_t)PTR_TO_REG(pCtx, A2);
diff --git a/src/coreclr/nativeaot/Runtime/riscv64/AllocFast.S b/src/coreclr/nativeaot/Runtime/riscv64/AllocFast.S
@@ -42,7 +42,7 @@
         // Determine whether the end of the object would lie outside of the current allocation context. If so,
         // we abandon the attempt to allocate the object directly and fall back to the slow helper.
         add   a2, a2, t3
-        ld    t4, OFFSETOF__Thread__m_alloc_context__alloc_limit(a1)
+        ld    t4, OFFSETOF__Thread__m_eeAllocContext__combined_limit(a1)
         bltu  t4, a2, LOCAL_LABEL(RhpNewFast_RarePath)
 
         // Update the alloc pointer to account for the allocation.
diff --git a/src/coreclr/nativeaot/Runtime/riscv64/AsmOffsetsCpu.h b/src/coreclr/nativeaot/Runtime/riscv64/AsmOffsetsCpu.h
@@ -17,8 +17,8 @@ PLAT_ASM_OFFSET(1C, ExInfo, m_idxCurClause)
 PLAT_ASM_OFFSET(20, ExInfo, m_frameIter)
 PLAT_ASM_OFFSET(348, ExInfo, m_notifyDebuggerSP)
 
-PLAT_ASM_OFFSET(0, PInvokeTransitionFrame, m_RIP)
-PLAT_ASM_OFFSET(8, PInvokeTransitionFrame, m_FramePointer)
+PLAT_ASM_OFFSET(0, PInvokeTransitionFrame, m_FramePointer)
+PLAT_ASM_OFFSET(8, PInvokeTransitionFrame, m_RIP)
 PLAT_ASM_OFFSET(10, PInvokeTransitionFrame, m_pThread)
 PLAT_ASM_OFFSET(18, PInvokeTransitionFrame, m_Flags)
 PLAT_ASM_OFFSET(20, PInvokeTransitionFrame, m_PreservedRegs)
@@ -52,7 +52,7 @@ PLAT_ASM_OFFSET(80, PAL_LIMITED_CONTEXT, IP)
 
 PLAT_ASM_SIZEOF(208, REGDISPLAY)
 
-PLAT_ASM_OFFSET(F8, REGDISPLAY, SP)
+PLAT_ASM_OFFSET(10, REGDISPLAY, SP)
 
 PLAT_ASM_OFFSET(48, REGDISPLAY, pS1)
 PLAT_ASM_OFFSET(90, REGDISPLAY, pS2)
diff --git a/src/coreclr/nativeaot/Runtime/riscv64/ExceptionHandling.S b/src/coreclr/nativeaot/Runtime/riscv64/ExceptionHandling.S
@@ -493,7 +493,7 @@ LOCAL_LABEL(NotHijacked):
         addi  t3, a5, OFFSETOF__Thread__m_ThreadStateFlags
 
         addiw  a6, zero, -17  // Mask value (0xFFFFFFEF)
-        amoand.w  a4, t3, a6
+        amoand.w  a4, a6, (t3)
 
         // Set preserved regs to the values expected by the funclet
         RESTORE_PRESERVED_REGISTERS a2
@@ -623,7 +623,7 @@ LOCAL_LABEL(NoAbort):
         // Set the DoNotTriggerGc flag
         addi  t3, a2, OFFSETOF__Thread__m_ThreadStateFlags
         addiw  a3, zero, -17  // Mask value (0xFFFFFFEF)
-        amoand.w  a4, t3, a3
+        amoand.w  a4, a3, (t3)
 
         // Restore preserved registers
         RESTORE_PRESERVED_REGISTERS a1
@@ -646,7 +646,7 @@ LOCAL_LABEL(NoAbort):
 
         addi  t3, a2, OFFSETOF__Thread__m_ThreadStateFlags
         addiw  a3, zero, 16  // Mask value (0x10)
-        amoor.w  a1, t3, a3
+        amoor.w  a1, a3, (t3)
 
         // Restore floating-point registers
         fld  fs0,  0x00(sp)
diff --git a/src/coreclr/nativeaot/Runtime/riscv64/WriteBarriers.S b/src/coreclr/nativeaot/Runtime/riscv64/WriteBarriers.S
@@ -261,7 +261,7 @@ LEAF_END RhpCheckedAssignRef, _TEXT
 // On exit:
 //  t3, t4 : trashed
 //  t6 : incremented by 8
-LEAF_ENTRY RhpAssignRefRiscVh64, _TEXT
+LEAF_ENTRY RhpAssignRefRiscV64, _TEXT
 
     ALTERNATE_ENTRY RhpAssignRefAVLocation
         sd    t6, 0(t5)
diff --git a/src/coreclr/nativeaot/Runtime/unix/UnwindHelpers.cpp b/src/coreclr/nativeaot/Runtime/unix/UnwindHelpers.cpp
@@ -1157,40 +1157,6 @@ inline uint64_t Registers_REGDISPLAY::getRegister(int regNum) const {
         return *pT5;
     case UNW_RISCV_X6:
         return *pT6;
-    case UNW_RISCV_X7:
-        return *pT7;
-    case UNW_RISCV_X8:
-        return *pT8;
-    case UNW_RISCV_X9:
-        return *pT9;
-    case UNW_RISCV_X10:
-        return *pT10;
-    case UNW_RISCV_X11:
-        return *pT11;
-    case UNW_RISCV_X12:
-        return *pT12;
-    case UNW_RISCV_X13:
-        return *pT13;
-    case UNW_RISCV_X14:
-        return *pT14;
-    case UNW_RISCV_X15:
-        return *pT15;
-    case UNW_RISCV_X16:
-        return *pT16;
-    case UNW_RISCV_X17:
-        return *pT17;
-    case UNW_RISCV_X18:
-        return *pT18;
-    case UNW_RISCV_X19:
-        return *pT19;
-    case UNW_RISCV_X20:
-        return *pT20;
-    case UNW_RISCV_X21:
-        return *pT21;
-    case UNW_RISCV_X22:
-        return *pT22;
-    case UNW_RISCV_X23:
-        return *pT23;
     // Add other general-purpose registers if needed
 
     case UNW_RISCV_F0:
@@ -1291,57 +1257,6 @@ void Registers_REGDISPLAY::setRegister(int regNum, uint64_t value, uint64_t loca
     case UNW_RISCV_X6:
         *pT6 = value;
         break;
-    case UNW_RISCV_X7:
-        *pT7 = value;
-        break;
-    case UNW_RISCV_X8:
-        *pT8 = value;
-        break;
-    case UNW_RISCV_X9:
-        *pT9 = value;
-        break;
-    case UNW_RISCV_X10:
-        *pT10 = value;
-        break;
-    case UNW_RISCV_X11:
-        *pT11 = value;
-        break;
-    case UNW_RISCV_X12:
-        *pT12 = value;
-        break;
-    case UNW_RISCV_X13:
-        *pT13 = value;
-        break;
-    case UNW_RISCV_X14:
-        *pT14 = value;
-        break;
-    case UNW_RISCV_X15:
-        *pT15 = value;
-        break;
-    case UNW_RISCV_X16:
-        *pT16 = value;
-        break;
-    case UNW_RISCV_X17:
-        *pT17 = value;
-        break;
-    case UNW_RISCV_X18:
-        *pT18 = value;
-        break;
-    case UNW_RISCV_X19:
-        *pT19 = value;
-        break;
-    case UNW_RISCV_X20:
-        *pT20 = value;
-        break;
-    case UNW_RISCV_X21:
-        *pT21 = value;
-        break;
-    case UNW_RISCV_X22:
-        *pT22 = value;
-        break;
-    case UNW_RISCV_X23:
-        *pT23 = value;
-        break;
 
     // Add other general-purpose registers if needed
 
