diff --git a/build/VSL.Imports.Closed.targets b/build/VSL.Imports.Closed.targets index 1376cc60e1d03..a853bdca6e337 100644 --- a/build/VSL.Imports.Closed.targets +++ b/build/VSL.Imports.Closed.targets @@ -1,4 +1,34 @@ + + + + + $(IntermediateOutputPath)$(TargetFileName).pcbm + + + + + + + + + + + + - + - - + + true + true + + + + + + + + + - $(CompileDependsOn);ApplyOptimizations - $(CleanDependsOn);CleanApplyOptimizations;CleanPhoneCopy + $(CleanDependsOn);CleanPhoneCopy - - true - true - $(CompileDependsOn);FakeSignAssembly - $(IntermediateOutputPath)$(TargetFileName).fakesign - - - - - - - - - $(CreateVsixContainerDependsOn);SignVsixInputs $(PrepareForRunDependsOn);SignVsix true - +